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2020-05-01lib: utils: Rename fdt_parse_clint() to fdt_parse_compat_addr()Anup Patel
The fdt_parse_clint() is quite generic and can be used for other types of devices so we rename it to fdt_parse_compat_addr(). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-29platform: Add Nuclei UX600 platformHuaqi Fang
* Nuclei UX600 is a 64-bit RISC-V core developed by Nuclei System Technology, see https://nucleisys.com/product.php * The ISA is configurable in hardware on your demand Signed-off-by: Huaqi Fang <578567190@qq.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-27lib: utils: Add SiFive test deviceAnup Patel
This patch factor-out SiFive test device related stuff into it's own source file from qemu/virt platform. In future, we can find SiFive test device address from device tree as well. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-27include: sbi_platform: Combine reboot and shutdown into one callbackAnup Patel
We can achieve shutdown, cold reboot, and warm reboot using just one sbi_platform callback so we combine system_reboot() and system_shutdown() callbacks into one system_reset() callback. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-27lib: No need to provide default PMP region using platform callbacksAnup Patel
The default (usually last) PMP region provides S-mode access to complete memory range not covered by other PMP regions. Currently, the default PMP region is described as platform specific PMP region which is not appropriate because all platforms need it and default PMP region should be part of generic library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-28platform: thead/c910: Use HSM extension to boot secondary coresLiu Yibin
Remove custom vendor extension and use HSM extension to boot secondary cores Signed-off-by: Liu Yibin <yibin_liu@c-sky.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-24platform: openpiton: Read the device configurations from device treeAtish Patra
OpenPiton is designed to run on different FPGAs with different configurations. Use the fdt parser to retrieve the required values from device tree instead of using fixed values. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-24lib: utils: Move fdt fixup helper routines to a different fileAtish Patra
FDT helper file contain both fdt fixup and parsing functions. Split the fixup related functions to a separate file for a better code organization. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-24platform: Add OpenPiton platform supportAtish Patra
OpenPiton is a research platform from Princeton University [1]. "OpenPiton is the world's first open source, general purpose, multithreaded manycore processor. It is a tiled manycore framework scalable from one to 1/2 billion cores." Add OpenSBI support for OpenPiton. As it is based on ariane core, it reuses the platform code from arine project. [1]. https://github.com/PrincetonUniversity/openpiton Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-24platform: fpga/ariane: Remove redundant plic address macrosAtish Patra
All the common PLIC specific macros are already defined in plic.c. Remove it from platform code. While at it, Fix the other coding style issues. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-24platform: Move ariane standalone fpga project to its own projectAtish Patra
Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-19platform: sifive/fu540: Remove FU540_ENABLED_HART_MASK optionAnup Patel
The FU540_ENABLED_HART_MASK compile time option was added for initial bring-up on SiFive Unleashed. This option is redundant now because disabled_hart_mask is already removed. Based on this rationale, we remove FU540_ENABLED_HART_MASK compile time option. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-19include: sbi_platform: Introduce HART index to HART id tableAnup Patel
A platform can have discontinuous and/or sparse HART ids so we cannot always assume a set of HARTs with continuous HART ids. This patch adds support for discontinuous and sparse HART ids by introducing HART index to HART id table. This table has platform hart_count entries and it maps HART index to HART id. The HART index to HART id table has only two restrictions: 1. HART index < sbi_platform hart_count 2. HART id < SBI_HARTMASK_MAX_BITS Example1: Let's say we have a platform with 2 HART ids 11 and 22, for such a a platform: hart_count = 2 hart_index2id[0] = 11 hart_index2id[1] = 22 Example2: Let's say we have a platform with 5 HARTs ids 0, 1, 2, 3, and 4 but out of these HART with id 0 is not usable so for such a platform: hart_count = 5 hart_index2id[0] = -1U hart_index2id[1] = 1 hart_index2id[2] = 2 hart_index2id[3] = 3 hart_index2id[4] = 4 OR hart_count = 4 hart_index2id[0] = 1 hart_index2id[1] = 2 hart_index2id[2] = 3 hart_index2id[3] = 4 With HART index to HART id table in place, the hart_disabled() callback is now redundant so we remove it as well. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-18platform: Update to call general DT fix-up helperBin Meng
Platform andes/ae350, ariane-fpga, qemu/virt and sifive/fu540 codes have been updated to call this general DT fix-up helper. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-18platform: sifive/fu540: Replace cpu0 node fix-up with the new helperBin Meng
This replaces the FU540 specific cpu0 node "status" property fix-up with the newly introduced generic fdt_cpu_fixup() helper. Unlike previous logic, the helper routine does not test the "mmu-type" property to determine which node we should fix up, instead it uses sbi_platform_hart_disabled() API. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-18platform: sifive/fu540: Remove "stdout-path" fix-upBin Meng
As of today the upstream U-Boot & Linux kernel ships a device tree that already has "stdout-path" properly set in the "/chosen" node. This is the same with the QEMU 'sifive_u' machine. Hence the codes to fix up the "stdout-path" in OpenSBI is not necessary. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-18platform: sifive/fu540: Fix up DT for reserved memoryBin Meng
This calls fdt_reserved_memory_fixup() helper in the platform's final_init() routine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-18platform: qemu/virt: Fix up DT for reserved memoryBin Meng
This calls fdt_reserved_memory_fixup() helper in the platform's final_init() routine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-18platform: ariane-fpga: Fix up DT for reserved memoryBin Meng
This calls fdt_reserved_memory_fixup() helper in the platform's final_init() routine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-18platform: andes/ae350: Fix up DT for reserved memoryBin Meng
This calls fdt_reserved_memory_fixup() helper in the platform's final_init() routine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-18lib: utils: Move PLIC DT fix up codes to fdt_helper.cBin Meng
Now that we have a dedicated fdt_helper.c file for DT releated helper routines, move plic_fdt_fixup() codes from plic.c to fdt_helper.c and rename it to fdt_plic_fixup() at the same time, to keep name consistency in the same file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-18platform: Clean up include header filesBin Meng
Adjust the order of include header files in alphabetical order in platform codes. Also remove unnecessary inclusions. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-14platform: Use one unified per-HART stack size macro for all platformsBin Meng
As of today all platforms use 8KB of per-HART stack hence there is no need for each platform to define its own macro or use the magic number. Create one macro for all platforms. Platform still can use its own version if needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-14platform: Set per-HART stack size to 8KB in the template platform codesBin Meng
The template platform codes should set per-HART stack size to 8KB to avoid possible mistakes of future platform ports. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-14platform: ariane-fpga: Set per-HART stack size to 8KBBin Meng
Recent commit 4a603eb ("platform: kendryte/k210: Set per-HART stack size to 8KB") forgot to update ariane-fpga codes, and the following commit 678c3c3 ("include: sbi_scratch: Set per-HART scratch size to 4KB") changed the per-HART scratch size to 4KB, which potentially breaks ariane-fpga platform. This patch set per-HART stack size of ariane-fpga to 8KB for consistency. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-13include: Make sbi_current_hartid() as macro in riscv_asm.hAnup Patel
The sbi_current_hartid() being a regular function is quite expensive because for callers it is a function call instead of a direct CSR read. This patch converts sbi_current_hartid() into a macro in riscv_asm.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-13platform: ariane-fpga: Change license for ariane-fpga from GPL-2.0 to BSD-2Panagiotis Peristerakis
Signed-off-by: Panagiotis Peristerakis <perister@ics.forth.gr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-11include: Remove disabled_hart_mask from sbi_platformAnup Patel
The disabled_hard_mask in sbi_platform is only 64bits wide so we cannot disable a HART with HARTID > 63. To tackle this, we remove disabled_hart_mask and replace it with hart_disabled() platform callback. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-10platform: ae350: Sort build objects in alphabetical orderBin Meng
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-08platform: kendryte/k210: Set per-HART stack size to 8KBAnup Patel
All platform except kendryte/k210 use 8KB of per-HART stack hence this patch set per-HART stack size of kendryte/k210 to 8KB for consistency. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-08platform: sifive: fu540: allow sv32 as an mmu-typeSören Tempel
There has already been a commit to master which added 32-bit specific fdt/payload addresses for the sifive/fu540 platform [0]. This commit introduces another change for using sifive/fu540 as a 32-bit platform. On 32-bit platforms, cores with the SV32 MMU type should not be disabled. For this reason, this commit also allows using this MMU type on the sifive/fu540 platform. Alternatively it would also be possible to only allow SV39 and SV48 if `__riscv_xlen == 64` and SV32 if `__riscv_xlen == 32`. Removing the check entirely would also be an option. [0]: 66fb729a1e46a9a46e809f3b7867fef91477e494 Signed-off-by: Sören Tempel <tempel@uni-bremen.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-02-19platform: qemu: virt: Correct the typo in config.mkBin Meng
It should be "aligned". Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-19platform: sifive: fu540: Add 32-bit specific fdt/payload addressesBin Meng
For testing 32-bit SiFive specific drivers with QEMU riscv32, add 32-bit specific FW_JUMP_FDT_ADDR and FW_PAYLOAD_OFFSET. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-17platform: Remove stale options from config.mk filesAnup Patel
This patch removes stale options from config.mk files of Ariane FPGA and QEMU virt platform support. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-17platform: Add Spike initial supportJames Clarke
This patch adds initial platform support Spike emulator. Signed-off-by: James Clarke <jrtc27@jrtc27.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-07platform: sifive: fu540: Add platform specific 'make run' cmdBin Meng
This adds sifive/fu540 specific QEMU run command. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-07platform: Drop qemu/sifive_u supportBin Meng
With QEMU v4.2 RISC-V changes to improve the emulation fidelity of 'sifive_u' machine, OpenSBI v0.4 / U-Boot v2019.10 / Linux kernel v5.3 images built for the SiFive HiFive Unleashed board can be used out of the box without any special hack. Hence there is no need for us to continue supporting such a special target in OpenSBI. Going forward, sifive/fu540 platform can be used on both real hardware and QEMU 'sifive_u' machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-05platform: sifive/fu540: Set tlb range flush limit to zeroAtish Patra
It was reported that tlb range flush is not working on fu540. Only tlb full flush seems to work on fu540 probably due to some hardware errata. Set the tlb flush limit to zero so that all tlb flush requests are converted to full flush. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-05platform: Add an platform ops to return platform specific tlb flush limitAtish Patra
If a platform requires to perform a tlb full flush, they should set the tlb_range_flush_limit value to zero. However, corresponding platform API ignore the value and continue to return the default value. Add a platform ops to retrieve platform specific tlb range flush limit. The platform variable becomes redundant in presence of the platform ops. Take this opportunity to remove the variable as well. The default is still set to smallest page size in RISC-V (4KB), as there is no way to figure out a best value for all platforms. Individual platform should set it to the optimal value for their platform. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-01-25platform: Update UART base addresses for qemu/sifve_uNikita Ermakov
In the QEMU [1] there was a change of the UART base addresses for sifive_u machine to match the hardware. Make corresponding changes in the opensbi for qemu/sifive_u platform. [1] https://git.qemu.org/?p=qemu.git;a=commitdiff;h=4b55bc2b5f7ff065da5d2b813ee5153c598d3764 Signed-off-by: Nikita Ermakov <coffe92@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-01-24platform: template: typo fix in system reboot/shutdown namesJiuyang Liu (Sequencer)
This patch does minor typo fix in system reboot/shutdown names in platform operations. Signed-off-by: Jiuyang Liu (Sequencer) <liujiuyang1994@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-01-15platform: thead/c910: Don't set plic/clint address in warm bootLiu Yibin
Since all harts share the same plic/clint address now, setting them during cold boot is just fine. Signed-off-by: Liu Yibin <yibin_liu@c-sky.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-01-15platform: thead/c910: Don't enable L2 cache in warm bootLiu Yibin
Since all harts share the same L2 cache now, there's no need to Enable L2 cache in warm boot. Signed-off-by: Liu Yibin <yibin_liu@c-sky.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-01-09platform: thead/c910: Remove SBI_PLATFORM_HAS_PMPLiu Yibin
T-head c910 is a generic FPGA platform so we cannot define PMP configuration for it in OpenSBI because PMP configuration tend to be SOC specific. Signed-off-by: Liu Yibin <yibin_liu@c-sky.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-02platform: Add T-head C910 initial supportLiu Yibin
This commit provides basic support for the Thead/C910 platform. Signed-off-by: Liu Yibin <yibin_liu@c-sky.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-01-02lib: utils: Support CLINT with 32bit MMIO access on RV64 systemAnup Patel
It is possible to have a CLINT implementation which supports only 32bit MMIO accesses on RV64 system so this patch extends our CLINT driver such that platform code can specify whether CLINT supports 64bit MMIO access. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra<atish.patra@wdc.com> Reviewed-by: Zong Li <zong.li@sifive.com>
2019-09-28kendryte/k210: remove unused fileDamien Le Moal
Commit 9dfe72057957 ("kendryte/k210: remove sysctl code") missed removing the file sysctl.c. Fix this here. Fixes: 9dfe72057957 ("kendryte/k210: remove sysctl code") Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-09-10lib: provide a platform specific tlb range flush thresholdAtish Patra
Currently, the tlb range flush threshold is fixed and set to 4k for all platforms. However, it should be platform specific as it completely depends upon how platform actually implements sfence instruction. Define a platform feature that allows every individual platform to set different values. If a platform doesn't define it, just use a page size as the threshold. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-09-05kendryte/k210: remove sysctl codeDamien Le Moal
Directly implement frequency discovery, making the sysctl code unnecessary. While at it, Move all macro definitions from platform.c into platform.h and cleanup that file, removing the need for the Apache 2.0 license and Canaan Inc copyright. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-09-05kendryte/k210: Use sifive UART driverDamien Le Moal
The Kendryte K210 UARTHS is compatible with SiFive UART. So use the sifive uart driver and remove the k210 uarths platform code. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
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