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authorAnup Patel <anup.patel@wdc.com>2020-03-12 10:21:25 +0530
committerAnup Patel <anup@brainfault.org>2020-03-13 12:22:02 +0530
commit823345ecaed0deb7770d9bac1c881004a6410e91 (patch)
treee3b71fb186be4bebd610e796cc12f2d3f33424e6 /platform
parent16e7071f6ddd5ba69d416b5a68e4aa191fc19d3b (diff)
include: Make sbi_current_hartid() as macro in riscv_asm.h
The sbi_current_hartid() being a regular function is quite expensive because for callers it is a function call instead of a direct CSR read. This patch converts sbi_current_hartid() into a macro in riscv_asm.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'platform')
-rw-r--r--platform/andes/ae350/platform.c4
-rw-r--r--platform/andes/ae350/plicsw.c12
-rw-r--r--platform/andes/ae350/plmt.c8
-rw-r--r--platform/ariane-fpga/platform.c3
-rw-r--r--platform/kendryte/k210/platform.c4
-rw-r--r--platform/qemu/virt/platform.c3
-rw-r--r--platform/sifive/fu540/platform.c6
-rw-r--r--platform/template/platform.c3
8 files changed, 23 insertions, 20 deletions
diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c
index 08db3eb..b85cec4 100644
--- a/platform/andes/ae350/platform.c
+++ b/platform/andes/ae350/platform.c
@@ -8,9 +8,9 @@
* Nylon Chen <nylon7@andestech.com>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
-#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
#include <sbi/sbi_console.h>
#include <sbi_utils/serial/uart8250.h>
@@ -94,7 +94,7 @@ static int ae350_console_init(void)
/* Initialize the platform interrupt controller for current HART. */
static int ae350_irqchip_init(bool cold_boot)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
int ret;
if (cold_boot) {
diff --git a/platform/andes/ae350/plicsw.c b/platform/andes/ae350/plicsw.c
index 17fe947..d07df28 100644
--- a/platform/andes/ae350/plicsw.c
+++ b/platform/andes/ae350/plicsw.c
@@ -8,9 +8,9 @@
* Nylon Chen <nylon7@andestech.com>
*/
-#include <sbi/sbi_types.h>
-#include <sbi/sbi_hart.h>
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_io.h>
+#include <sbi/sbi_types.h>
#include "plicsw.h"
#include "platform.h"
@@ -19,7 +19,7 @@ static struct plicsw plicsw_dev[AE350_HART_COUNT];
static inline void plicsw_claim(void)
{
- u32 source_hart = sbi_current_hartid();
+ u32 source_hart = current_hartid();
plicsw_dev[source_hart].source_id =
readl(plicsw_dev[source_hart].plicsw_claim);
@@ -27,7 +27,7 @@ static inline void plicsw_claim(void)
static inline void plicsw_complete(void)
{
- u32 source_hart = sbi_current_hartid();
+ u32 source_hart = current_hartid();
u32 source = plicsw_dev[source_hart].source_id;
writel(source, plicsw_dev[source_hart].plicsw_claim);
@@ -61,7 +61,7 @@ static inline void plic_sw_pending(u32 target_hart)
* The bit 5 is used to send IPI to hart 2
* The bit 4 is used to send IPI to hart 3
*/
- u32 source_hart = sbi_current_hartid();
+ u32 source_hart = current_hartid();
u32 target_offset = (PLICSW_PENDING_PER_HART - 1) - target_hart;
u32 per_hart_offset = PLICSW_PENDING_PER_HART * source_hart;
u32 val = 1 << target_offset << per_hart_offset;
@@ -90,7 +90,7 @@ void plicsw_ipi_clear(u32 target_hart)
int plicsw_warm_ipi_init(void)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (!plicsw_dev[hartid].plicsw_pending
&& !plicsw_dev[hartid].plicsw_enable
diff --git a/platform/andes/ae350/plmt.c b/platform/andes/ae350/plmt.c
index db80813..3848e15 100644
--- a/platform/andes/ae350/plmt.c
+++ b/platform/andes/ae350/plmt.c
@@ -8,8 +8,8 @@
* Nylon Chen <nylon7@andestech.com>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_io.h>
-#include <sbi/sbi_hart.h>
static u32 plmt_time_hart_count;
static volatile void *plmt_time_base;
@@ -34,7 +34,7 @@ u64 plmt_timer_value(void)
void plmt_timer_event_stop(void)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart)
return;
@@ -50,7 +50,7 @@ void plmt_timer_event_stop(void)
void plmt_timer_event_start(u64 next_event)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart)
return;
@@ -70,7 +70,7 @@ void plmt_timer_event_start(u64 next_event)
int plmt_warm_timer_init(void)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart || !plmt_time_base)
return -1;
diff --git a/platform/ariane-fpga/platform.c b/platform/ariane-fpga/platform.c
index d5d0fbc..cc8429b 100644
--- a/platform/ariane-fpga/platform.c
+++ b/platform/ariane-fpga/platform.c
@@ -4,6 +4,7 @@
* Panagiotis Peristerakis <perister@ics.forth.gr>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
#include <sbi/sbi_platform.h>
@@ -105,7 +106,7 @@ static int plic_ariane_warm_irqchip_init(u32 target_hart,
*/
static int ariane_irqchip_init(bool cold_boot)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
int ret;
if (cold_boot) {
diff --git a/platform/kendryte/k210/platform.c b/platform/kendryte/k210/platform.c
index 1b49b39..00b38f7 100644
--- a/platform/kendryte/k210/platform.c
+++ b/platform/kendryte/k210/platform.c
@@ -7,9 +7,9 @@
* Damien Le Moal <damien.lemoal@wdc.com>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
-#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
#include <sbi/sbi_console.h>
#include <sbi_utils/irqchip/plic.h>
@@ -55,7 +55,7 @@ static int k210_console_init(void)
static int k210_irqchip_init(bool cold_boot)
{
int rc;
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (cold_boot) {
rc = plic_cold_irqchip_init(K210_PLIC_BASE_ADDR,
diff --git a/platform/qemu/virt/platform.c b/platform/qemu/virt/platform.c
index d2c841c..fdc5a2c 100644
--- a/platform/qemu/virt/platform.c
+++ b/platform/qemu/virt/platform.c
@@ -8,6 +8,7 @@
* Nick Kossifidis <mick@ics.forth.gr>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_const.h>
@@ -84,7 +85,7 @@ static int virt_console_init(void)
static int virt_irqchip_init(bool cold_boot)
{
int rc;
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (cold_boot) {
rc = plic_cold_irqchip_init(
diff --git a/platform/sifive/fu540/platform.c b/platform/sifive/fu540/platform.c
index 4a8c016..848261c 100644
--- a/platform/sifive/fu540/platform.c
+++ b/platform/sifive/fu540/platform.c
@@ -9,12 +9,12 @@
#include <libfdt.h>
#include <fdt.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_io.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
-#include <sbi/sbi_hart.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_platform.h>
-#include <sbi/riscv_io.h>
#include <sbi_utils/irqchip/plic.h>
#include <sbi_utils/serial/sifive-uart.h>
#include <sbi_utils/sys/clint.h>
@@ -148,7 +148,7 @@ static int fu540_console_init(void)
static int fu540_irqchip_init(bool cold_boot)
{
int rc;
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (cold_boot) {
rc = plic_cold_irqchip_init(FU540_PLIC_ADDR,
diff --git a/platform/template/platform.c b/platform/template/platform.c
index c98bbff..60b65ea 100644
--- a/platform/template/platform.c
+++ b/platform/template/platform.c
@@ -4,6 +4,7 @@
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
#include <sbi/sbi_platform.h>
@@ -82,7 +83,7 @@ static int platform_console_getc(void)
*/
static int platform_irqchip_init(bool cold_boot)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
int ret;
/* Example if the generic PLIC driver is used */
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-06 14:53:04 +0000