diff options
| author | Xiang W <wxjstz@126.com> | 2021-04-01 15:59:40 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-04-05 13:43:08 +0530 |
| commit | 3d8a952737935dd98200b05b68dacb5e94071877 (patch) | |
| tree | 0e641519f65664f3f05deada0cf547c64037e08c /include | |
| parent | 4ef2f5d3e6b25356a8fab19574bed76ce60edeee (diff) | |
lib: fix csr detect support
csr_read_allowed/csr_read_allowed requires trap.case to detect the results,
but if no exception occurs, the value of trap.case will remain unchanged,
which makes the detection results unreliable. Add code to initialize
trap.case to 0.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/sbi_csr_detect.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/sbi/sbi_csr_detect.h b/include/sbi/sbi_csr_detect.h index f294888..89ba294 100644 --- a/include/sbi/sbi_csr_detect.h +++ b/include/sbi/sbi_csr_detect.h @@ -12,6 +12,7 @@ #include <sbi/riscv_encoding.h> #include <sbi/sbi_hart.h> +#include <sbi/sbi_trap.h> #define csr_read_allowed(csr_num, trap) \ ({ \ @@ -19,6 +20,7 @@ register ulong ttmp asm("a4"); \ register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong ret = 0; \ + ((struct sbi_trap_info *)(trap))->cause = 0; \ asm volatile( \ "add %[ttmp], %[tinfo], zero\n" \ "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \ @@ -36,6 +38,7 @@ register ulong tinfo asm("a3") = (ulong)trap; \ register ulong ttmp asm("a4"); \ register ulong mtvec = sbi_hart_expected_trap_addr(); \ + ((struct sbi_trap_info *)(trap))->cause = 0; \ asm volatile( \ "add %[ttmp], %[tinfo], zero\n" \ "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \ |