From 3d8a952737935dd98200b05b68dacb5e94071877 Mon Sep 17 00:00:00 2001
From: Xiang W <wxjstz@126.com>
Date: Thu, 1 Apr 2021 15:59:40 +0800
Subject: lib: fix csr detect support
csr_read_allowed/csr_read_allowed requires trap.case to detect the results,
but if no exception occurs, the value of trap.case will remain unchanged,
which makes the detection results unreliable. Add code to initialize
trap.case to 0.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
include/sbi/sbi_csr_detect.h | 3 +++
1 file changed, 3 insertions(+)
(limited to 'include')
diff --git a/include/sbi/sbi_csr_detect.h b/include/sbi/sbi_csr_detect.h
index f294888..89ba294 100644
--- a/include/sbi/sbi_csr_detect.h
+++ b/include/sbi/sbi_csr_detect.h
@@ -12,6 +12,7 @@
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_hart.h>
+#include <sbi/sbi_trap.h>
#define csr_read_allowed(csr_num, trap) \
({ \
@@ -19,6 +20,7 @@
register ulong ttmp asm("a4"); \
register ulong mtvec = sbi_hart_expected_trap_addr(); \
register ulong ret = 0; \
+ ((struct sbi_trap_info *)(trap))->cause = 0; \
asm volatile( \
"add %[ttmp], %[tinfo], zero\n" \
"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
@@ -36,6 +38,7 @@
register ulong tinfo asm("a3") = (ulong)trap; \
register ulong ttmp asm("a4"); \
register ulong mtvec = sbi_hart_expected_trap_addr(); \
+ ((struct sbi_trap_info *)(trap))->cause = 0; \
asm volatile( \
"add %[ttmp], %[tinfo], zero\n" \
"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
--
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