diff options
| author | NIIBE Yutaka <gniibe@fsij.org> | 2015-07-29 17:06:17 +0900 |
|---|---|---|
| committer | NIIBE Yutaka <gniibe@fsij.org> | 2015-07-29 17:06:17 +0900 |
| commit | a9de53c36be5ca31974cbf3c7903ca5cf7f7fff2 (patch) | |
| tree | 0ff6c70ab4d493e907d5f4f1e8ee8584580bde8b /board/board-stm8s-discovery.h | |
| parent | 83486efd5f7857e539c79ed9c947cec854468240 (diff) | |
board update, adding ST Dongle
Diffstat (limited to 'board/board-stm8s-discovery.h')
| -rw-r--r-- | board/board-stm8s-discovery.h | 35 |
1 files changed, 17 insertions, 18 deletions
diff --git a/board/board-stm8s-discovery.h b/board/board-stm8s-discovery.h index 002daca..80deb75 100644 --- a/board/board-stm8s-discovery.h +++ b/board/board-stm8s-discovery.h @@ -1,7 +1,6 @@ #define BOARD_NAME "STM8S Discovery" #define BOARD_ID 0x2f0976bb -#define FLASH_PAGE_SIZE 1024 #define STM32F10X_MD /* Medium-density device */ #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 @@ -10,25 +9,9 @@ #define GPIO_LED_BASE GPIOA_BASE #define GPIO_LED_SET_TO_EMIT 8 -#undef GPIO_USB_BASE -#undef GPIO_USB_CLEAR_TO_ENABLE +#undef GPIO_USB_BASE /* No external DISCONNECT/RENUM circuit. */ #define GPIO_OTHER_BASE GPIOB_BASE -/* For pin-cir settings of Gnuk */ -#define TIMx TIM3 -#define INTR_REQ_TIM TIM3_IRQ -#define AFIO_EXTICR_INDEX 1 -#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR2_EXTI5_PB -#define EXTI_PR EXTI_PR_PR5 -#define EXTI_IMR EXTI_IMR_MR5 -#define EXTI_FTSR_TR EXTI_FTSR_TR5 -#define INTR_REQ_EXTI EXTI9_5_IRQ -#define ENABLE_RCC_APB1 -#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM3EN -#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM3RST -#define AFIO_MAPR_SOMETHING AFIO_MAPR_TIM3_REMAP_PARTIALREMAP - /* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */ - /* * Port A setup. * PA0 - input with pull-up. AN0 @@ -58,3 +41,19 @@ #define VAL_GPIO_OTHER_ODR 0xFFFFFFFE #define VAL_GPIO_OTHER_CRL 0x88888888 /* PB7...PB0 */ #define VAL_GPIO_OTHER_CRH 0x88888888 /* PB15...PB8 */ + + +/* For pin-cir settings of Gnuk */ +#define TIMx TIM3 +#define INTR_REQ_TIM TIM3_IRQ +#define AFIO_EXTICR_INDEX 1 +#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR2_EXTI5_PB +#define EXTI_PR EXTI_PR_PR5 +#define EXTI_IMR EXTI_IMR_MR5 +#define EXTI_FTSR_TR EXTI_FTSR_TR5 +#define INTR_REQ_EXTI EXTI9_5_IRQ +#define ENABLE_RCC_APB1 +#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM3EN +#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM3RST +#define AFIO_MAPR_SOMETHING AFIO_MAPR_TIM3_REMAP_PARTIALREMAP + /* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */ |