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| author | NIIBE Yutaka <gniibe@fsij.org> | 2013-11-26 17:01:15 +0900 |
|---|---|---|
| committer | NIIBE Yutaka <gniibe@fsij.org> | 2013-11-26 17:01:15 +0900 |
| commit | 2327cd9013d6594def9486d890146e2c208cf5fa (patch) | |
| tree | 60fc6081c1b4ef11a4b97de9eef93a910cbd3a15 | |
| parent | 5968e2a0539280c9f61e75bbf8bc78711c0d8496 (diff) | |
add STBee support
| -rw-r--r-- | ChangeLog | 2 | ||||
| -rw-r--r-- | NEWS | 7 | ||||
| -rw-r--r-- | board/board-stbee.h | 42 |
3 files changed, 51 insertions, 0 deletions
@@ -1,5 +1,7 @@ 2013-11-26 Niibe Yutaka <gniibe@fsij.org> + * board/board-stbee.h: New. + * rules.mk (OUTFILES) [ENABLE_OUTPUT_HEX]: Add hex generation. 2013-11-21 Niibe Yutaka <gniibe@fsij.org> @@ -1,5 +1,12 @@ NEWS - Noteworthy changes +* Major changes in Chopstx 0.04 + + Released 2013-12-XX, by NIIBE Yutaka + +** Board support STBEE +The board STBEE is now supported. + * Major changes in Chopstx 0.03 Released 2013-11-08, by NIIBE Yutaka diff --git a/board/board-stbee.h b/board/board-stbee.h new file mode 100644 index 0000000..6c1f313 --- /dev/null +++ b/board/board-stbee.h @@ -0,0 +1,42 @@ +#define FLASH_PAGE_SIZE 2048 + +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 6 +#define STM32_HSECLK 12000000 + +#define GPIO_USB_CLEAR_TO_ENABLE 3 +#define GPIO_LED_CLEAR_TO_EMIT 4 + +/* + * Port A setup. + * PA0 - Normal input. + * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) + * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP) + */ +#define VAL_GPIO_OTHER_ODR 0xFFFFE7FF +#define VAL_GPIO_OTHER_CRL 0x88888884 /* PA7...PA0 */ +#define VAL_GPIO_OTHER_CRH 0x88811888 /* PA15...PA8 */ + +#define RCC_APB2ENR_IOP_EN (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPDEN) +#define RCC_APB2RSTR_IOP_RST (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPDRST) + +/* + * Port D setup. + * PD3 - Push pull output (USB_DISC 1:USB-DISABLE 0:USB-ENABLE) 2MHz + * PD4 - Open Drain output 2MHz (LED1). + */ +#define VAL_GPIO_ODR 0xFFFFFFFF +#define VAL_GPIO_CRL 0x88862888 /* PD7...PD0 */ +#define VAL_GPIO_CRH 0x88888888 /* PD15...PD8 */ + +#define GPIO_USB_BASE GPIOD_BASE +#define GPIO_LED_BASE GPIOD_BASE +#define GPIO_OTHER_BASE GPIOA_BASE + +/* NeuG settings for ADC2. */ +#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \ + | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5) +#define NEUG_ADC_SETTING2_SMPR2 0 +#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) \ + | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11) +#define NEUG_ADC_SETTING2_NUM_CHANNELS 2 |