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This driver is for T-HEAD test chip, fpga. It could work with
all T-HEAD riscv processors: C9xx series.
example1: (Using io-regs for reset)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
entry-reg = <0xff 0xff019050>;
entry-cnt = <4>;
control-reg = <0xff 0xff015004>;
control-val = <0x1c>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
};
example2: (Using csr-regs for reset)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
using-csr-reset;
csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
0x3b0 0x3b1 0x3b2 0x3b3
0x3b4 0x3b5 0x3b6 0x3b7
0x3a0>;
};
example3: (Only delegate plic enable to S-mode)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
};
After this patch, all T-HEAD c9xx would use platform/generic with fw_dynamic
as default:
CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make
The platform/thead will be deprecated.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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GCC has already a predefined macro __ASSEMBLER__ therefore, it can be
used without the need to define a new flag with -D__ASSEMBLY__.
This is useful when adding the library to projects having a build
system such one can build without the need to make changes.
THe build system does not use the Makefile in the sources tree.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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We extend sbi_hart_pmp_check_addr() API so that users can specify
privilege mode of the address for checking PMP access permissions.
To achieve this, we end-up converting "unsigned long *size" parameter
to "unsigned long *log2len" for pmp_get() implementation so that we
can deal with regions of "1UL << __riscv_xlen" size in a special case
in sbi_hart_pmp_check_addr() implementation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The RISC-V ISA string does not follow alphabetical order. Instead,
we have a RISC-V specific ordering of extensions in the RISC-V ISA
string. This patch improves misa_string() implementation to return
a valid RISC-V ISA string.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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Currently pmp_get() returns the log2 length of the PMP memory
region size. The caller has to calculate the size based on that
and the same codes are duplicated.
Update this function to return decoded size directly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The sbi_current_hartid() being a regular function is quite
expensive because for callers it is a function call instead
of a direct CSR read. This patch converts sbi_current_hartid()
into a macro in riscv_asm.h.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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This fixes various coding style issues found in the SBI codes.
No functional changes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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The right location for all bits related defines and macros is
sbi_bitops.h hence this patch. With this patch, the sbi_bits.h
is redundant so we remove it.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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Add assertions for misa_extension to prevent incoming illegal
characters.
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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On some platforms, misa may not be implemented. On such a platform,
reading misa will get 0. At this time, platform is required to
implement a non-standard function to detect the CPU's capabilities.
Therefore, this modification add interfaces for non-standard function.
The MXL field of misa is always at the highest two bits, whether it
is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification
fixes the use of a fixed offset to detect the machine length.
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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This patch factor-out TLB management from IPI management to separate
sources sbi_tlb.c and sbi_tlb.h.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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On latest Linux kernel (i.e. 5.2-rc1), we get large TLB flush
request for user space addresses (typically, start=x and end=-1).
This is caused by Linux kernel commit a21344dfc6 ("riscv: fix
sbi_remote_sfence_vma{,_asid}").
It's not practical to execute large number of sfence instructions
for a large TLB flush range because it takes too much time and
eventually causes CPU stall in Linux kernel.
This patch addresses above issue by upgrading TLB flush range to
TLB flush all whenever TLB flush range is greater than 1GB.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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Noisy commit, no functional changes.
Generated with an current upstream clang-format and:
clang-format -i $(find . -name \*.[ch])
Signed-off-by: Olof Johansson <olof@lixom.net>
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One of the shortcomings of clang-format is that it doesn't allow
for aligned define tables, which is used for a number of constants.
Add annotation to disable the automatic formatting where needed.
Signed-off-by: Olof Johansson <olof@lixom.net>
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Currently, OpenSBI doesn't distinguish between sfence.vma
and sfence.vm asid calls. Moreover, it ignores the page
ranges and just flush entire TLB everytime.
Fix the sfence implementation by keeping all the tlb flush
info in scratch area.
The relevant Linux kernel code was added by
https://patchwork.kernel.org/project/linux-riscv/list/?series=89695
However, this patch is backward compatible with older version kernel
that doesn't have the above patches as well.
Fixes #87
Signed-off-by: Atish Patra <atish.patra@wdc.com>
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Some toolchains might not have all the CSRs available (as seen with
GCC 7.2). So, instead use the defined CSR_ values.
Signed-off-by: Olof Johansson <olof@lixom.net>
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This patch updates copyright header in all files as follows:
1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line
2. Change copyright year to 2019 for Western Digital
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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Add addtional functionlities for set/clear bits
atomically.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
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The struct sbi_trap_regs related defines RISCV_TRAP_REGS_xyz should
be in sbi_trap.h so that we can keep these defines in-sync with changes
in struct sbi_trap_regs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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The struct sbi_platform related defines RISCV_PLATFORM_xyz should
be in sbi_platform.h so that we can keep these defines in-sync
with changes in struct sbi_platform.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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The struct sbi_scratch related defines RISCV_SCRATCH_xyz should
be in sbi_scratch.h so that we can keep these defines in-sync
with changes in struct sbi_scratch.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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We replace #csr with __ASM_STR(csr) in all csr_xyz() macros
so that we can pass CSR number instead of CSR name when GCC
is not aware of CSR name.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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The patch removes redundant csr_read_n() and csr_write_n()
because same thing can be achieved by using __ASM_STR()
macro in csr_read() and csr_write() macros.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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The hart_count and hart_stack_size information is already available
in "struct sbi_platform" so we use that instead of depending on
PLAT_HART_COUNT and PLAT_HART_STACK_SIZE.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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Signed-off-by: Anup Patel <anup.patel@wdc.com>
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