diff options
| author | Anup Patel <anup.patel@wdc.com> | 2020-03-04 11:08:35 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-03-08 11:06:18 +0530 |
| commit | 00d332bbe726d85e4c2b81ab0a08182612f96c03 (patch) | |
| tree | 7e0a75570a8b92bff0d74b2141869ce99dd7171a /include/sbi/riscv_asm.h | |
| parent | 8c83fb2fc8ef0c356f291a7e6517dad70a759981 (diff) | |
include: Move bits related defines and macros to sbi_bitops.h
The right location for all bits related defines and macros is
sbi_bitops.h hence this patch. With this patch, the sbi_bits.h
is redundant so we remove it.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'include/sbi/riscv_asm.h')
| -rw-r--r-- | include/sbi/riscv_asm.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h index c3d5985..63df3fc 100644 --- a/include/sbi/riscv_asm.h +++ b/include/sbi/riscv_asm.h @@ -38,7 +38,6 @@ #define LGREG __REG_SEL(3, 2) #if __SIZEOF_POINTER__ == 8 -#define BITS_PER_LONG 64 #ifdef __ASSEMBLY__ #define RISCV_PTR .dword #define RISCV_SZPTR 8 @@ -49,7 +48,6 @@ #define RISCV_LGPTR "3" #endif #elif __SIZEOF_POINTER__ == 4 -#define BITS_PER_LONG 32 #ifdef __ASSEMBLY__ #define RISCV_PTR .word #define RISCV_SZPTR 4 |