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authorAnup Patel <anup.patel@wdc.com>2020-03-04 11:08:35 +0530
committerAnup Patel <anup@brainfault.org>2020-03-08 11:06:18 +0530
commit00d332bbe726d85e4c2b81ab0a08182612f96c03 (patch)
tree7e0a75570a8b92bff0d74b2141869ce99dd7171a
parent8c83fb2fc8ef0c356f291a7e6517dad70a759981 (diff)
include: Move bits related defines and macros to sbi_bitops.h
The right location for all bits related defines and macros is sbi_bitops.h hence this patch. With this patch, the sbi_bits.h is redundant so we remove it. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat
-rw-r--r--include/sbi/riscv_asm.h2
-rw-r--r--include/sbi/sbi_bitops.h19
-rw-r--r--include/sbi/sbi_bits.h19
-rw-r--r--lib/sbi/riscv_atomic.c9
-rw-r--r--lib/sbi/sbi_emulate_csr.c2
-rw-r--r--lib/sbi/sbi_hart.c2
-rw-r--r--lib/sbi/sbi_hsm.c2
-rw-r--r--lib/sbi/sbi_illegal_insn.c2
-rw-r--r--lib/sbi/sbi_system.c1
-rw-r--r--lib/sbi/sbi_unpriv.c2
10 files changed, 27 insertions, 33 deletions
diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h
index c3d5985..63df3fc 100644
--- a/include/sbi/riscv_asm.h
+++ b/include/sbi/riscv_asm.h
@@ -38,7 +38,6 @@
#define LGREG __REG_SEL(3, 2)
#if __SIZEOF_POINTER__ == 8
-#define BITS_PER_LONG 64
#ifdef __ASSEMBLY__
#define RISCV_PTR .dword
#define RISCV_SZPTR 8
@@ -49,7 +48,6 @@
#define RISCV_LGPTR "3"
#endif
#elif __SIZEOF_POINTER__ == 4
-#define BITS_PER_LONG 32
#ifdef __ASSEMBLY__
#define RISCV_PTR .word
#define RISCV_SZPTR 4
diff --git a/include/sbi/sbi_bitops.h b/include/sbi/sbi_bitops.h
index 9d99299..10c29f1 100644
--- a/include/sbi/sbi_bitops.h
+++ b/include/sbi/sbi_bitops.h
@@ -10,8 +10,23 @@
#ifndef __SBI_BITOPS_H__
#define __SBI_BITOPS_H__
-#include <sbi/sbi_bits.h>
-#include <sbi/riscv_asm.h>
+#include <sbi/sbi_types.h>
+
+#if __SIZEOF_POINTER__ == 8
+#define BITS_PER_LONG 64
+#elif __SIZEOF_POINTER__ == 4
+#define BITS_PER_LONG 32
+#else
+#error "Unexpected __SIZEOF_POINTER__"
+#endif
+
+#define EXTRACT_FIELD(val, which) \
+ (((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) \
+ (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
+#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
/**
* ffs - Find first bit set
diff --git a/include/sbi/sbi_bits.h b/include/sbi/sbi_bits.h
deleted file mode 100644
index 3963d84..0000000
--- a/include/sbi/sbi_bits.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Authors:
- * Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __SBI_BITS_H__
-#define __SBI_BITS_H__
-
-#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
-#define INSERT_FIELD(val, which, fieldval) \
- (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
-
-#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
-#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
-#endif
diff --git a/lib/sbi/riscv_atomic.c b/lib/sbi/riscv_atomic.c
index 8b85801..9d8199e 100644
--- a/lib/sbi/riscv_atomic.c
+++ b/lib/sbi/riscv_atomic.c
@@ -7,11 +7,10 @@
* Anup Patel <anup.patel@wdc.com>
*/
-#include <sbi/sbi_types.h>
+#include <sbi/sbi_bitops.h>
#include <sbi/riscv_asm.h>
#include <sbi/riscv_atomic.h>
#include <sbi/riscv_barrier.h>
-#include <sbi/sbi_bits.h>
long atomic_read(atomic_t *atom)
{
@@ -209,12 +208,12 @@ unsigned long atomic_raw_xchg_ulong(volatile unsigned long *ptr,
#endif
}
-#if (BITS_PER_LONG == 64)
+#if (__SIZEOF_POINTER__ == 8)
#define __AMO(op) "amo" #op ".d"
-#elif (BITS_PER_LONG == 32)
+#elif (__SIZEOF_POINTER__ == 4)
#define __AMO(op) "amo" #op ".w"
#else
-#error "Unexpected BITS_PER_LONG"
+#error "Unexpected __SIZEOF_POINTER__"
#endif
#define __atomic_op_bit_ord(op, mod, nr, addr, ord) \
diff --git a/lib/sbi/sbi_emulate_csr.c b/lib/sbi/sbi_emulate_csr.c
index 0901ec1..dbb36cb 100644
--- a/lib/sbi/sbi_emulate_csr.c
+++ b/lib/sbi/sbi_emulate_csr.c
@@ -9,7 +9,7 @@
#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_emulate_csr.h>
#include <sbi/sbi_error.h>
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 535fe19..bce2fb5 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -12,7 +12,7 @@
#include <sbi/riscv_encoding.h>
#include <sbi/riscv_fp.h>
#include <sbi/riscv_locks.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_error.h>
#include <sbi/sbi_hart.h>
diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c
index 250cc7c..c1fd950 100644
--- a/lib/sbi/sbi_hsm.c
+++ b/lib/sbi/sbi_hsm.c
@@ -11,7 +11,7 @@
#include <sbi/riscv_barrier.h>
#include <sbi/riscv_encoding.h>
#include <sbi/riscv_atomic.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_error.h>
#include <sbi/sbi_ecall_interface.h>
diff --git a/lib/sbi/sbi_illegal_insn.c b/lib/sbi/sbi_illegal_insn.c
index e3c7809..413123d 100644
--- a/lib/sbi/sbi_illegal_insn.c
+++ b/lib/sbi/sbi_illegal_insn.c
@@ -9,7 +9,7 @@
#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
#include <sbi/sbi_emulate_csr.h>
#include <sbi/sbi_error.h>
#include <sbi/sbi_illegal_insn.h>
diff --git a/lib/sbi/sbi_system.c b/lib/sbi/sbi_system.c
index c6aa36c..68fad0f 100644
--- a/lib/sbi/sbi_system.c
+++ b/lib/sbi/sbi_system.c
@@ -8,6 +8,7 @@
* Nick Kossifidis <mick@ics.forth.gr>
*/
+#include <sbi/sbi_bitops.h>
#include <sbi/sbi_hart.h>
#include <sbi/sbi_hsm.h>
#include <sbi/sbi_platform.h>
diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c
index 07ef4a9..77ff2e9 100644
--- a/lib/sbi/sbi_unpriv.c
+++ b/lib/sbi/sbi_unpriv.c
@@ -8,7 +8,7 @@
*/
#include <sbi/riscv_encoding.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
#include <sbi/sbi_hart.h>
#include <sbi/sbi_scratch.h>
#include <sbi/sbi_trap.h>
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-17 22:03:57 +0000