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-rw-r--r--include/sbi/riscv_asm.h5
-rw-r--r--include/sbi/riscv_barrier.h3
2 files changed, 8 insertions, 0 deletions
diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h
index 9fa0fe5..1ff36de 100644
--- a/include/sbi/riscv_asm.h
+++ b/include/sbi/riscv_asm.h
@@ -157,6 +157,11 @@ void csr_write_num(int csr_num, unsigned long val);
__asm__ __volatile__("wfi" ::: "memory"); \
} while (0)
+#define ebreak() \
+ do { \
+ __asm__ __volatile__("ebreak" ::: "memory"); \
+ } while (0)
+
/* Get current HART id */
#define current_hartid() ((unsigned int)csr_read(CSR_MHARTID))
diff --git a/include/sbi/riscv_barrier.h b/include/sbi/riscv_barrier.h
index 905ecb4..1fba8b8 100644
--- a/include/sbi/riscv_barrier.h
+++ b/include/sbi/riscv_barrier.h
@@ -18,6 +18,9 @@
#define RISCV_FENCE(p, s) \
__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
+#define RISCV_FENCE_I \
+ __asm__ __volatile__ ("fence.i" : : : "memory")
+
/* Read & Write Memory barrier */
#define mb() RISCV_FENCE(iorw,iorw)