diff options
| author | Guo Ren <guoren@linux.alibaba.com> | 2021-04-17 16:26:17 +0000 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-04-22 15:13:53 +0530 |
| commit | 49e422c5ad7abee9be0bb1066b1db65676e61985 (patch) | |
| tree | 2eb84bb09b6e72726af4050089596bba2c27c7f7 /include | |
| parent | c5d064505236d8c272fffcd58fb27482325e14fd (diff) | |
lib: utils: reset: Add T-HEAD sample platform reset driver
This driver is for T-HEAD test chip, fpga. It could work with
all T-HEAD riscv processors: C9xx series.
example1: (Using io-regs for reset)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
entry-reg = <0xff 0xff019050>;
entry-cnt = <4>;
control-reg = <0xff 0xff015004>;
control-val = <0x1c>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
};
example2: (Using csr-regs for reset)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
using-csr-reset;
csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
0x3b0 0x3b1 0x3b2 0x3b3
0x3b4 0x3b5 0x3b6 0x3b7
0x3a0>;
};
example3: (Only delegate plic enable to S-mode)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
};
After this patch, all T-HEAD c9xx would use platform/generic with fw_dynamic
as default:
CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make
The platform/thead will be deprecated.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_asm.h | 5 | ||||
| -rw-r--r-- | include/sbi/riscv_barrier.h | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h index 9fa0fe5..1ff36de 100644 --- a/include/sbi/riscv_asm.h +++ b/include/sbi/riscv_asm.h @@ -157,6 +157,11 @@ void csr_write_num(int csr_num, unsigned long val); __asm__ __volatile__("wfi" ::: "memory"); \ } while (0) +#define ebreak() \ + do { \ + __asm__ __volatile__("ebreak" ::: "memory"); \ + } while (0) + /* Get current HART id */ #define current_hartid() ((unsigned int)csr_read(CSR_MHARTID)) diff --git a/include/sbi/riscv_barrier.h b/include/sbi/riscv_barrier.h index 905ecb4..1fba8b8 100644 --- a/include/sbi/riscv_barrier.h +++ b/include/sbi/riscv_barrier.h @@ -18,6 +18,9 @@ #define RISCV_FENCE(p, s) \ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") +#define RISCV_FENCE_I \ + __asm__ __volatile__ ("fence.i" : : : "memory") + /* Read & Write Memory barrier */ #define mb() RISCV_FENCE(iorw,iorw) |