diff options
| author | Xiang Wang <wxjstz@126.com> | 2019-03-04 17:22:37 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-03-05 09:09:40 +0530 |
| commit | 05602e2bf4812533adcb7acb1a67e43726c0e7bb (patch) | |
| tree | 6113a92fc9c35c1a57b138fd7966c83ab3ee66b7 /firmware/fw_base.S | |
| parent | 1c87f0f9b1952ba9770345fc8781ce3bd2d4de7c (diff) | |
firmware: Add a barrier instruction for wait for boot hart
Multi-core communication via memory requires the addition of a barrier
instructions to ensure cache coherency.
Signed-off-by: Xiang Wang <wxjstz@126.com>
Diffstat (limited to 'firmware/fw_base.S')
| -rw-r--r-- | firmware/fw_base.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index b28cfb5..ae14cc7 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -114,6 +114,7 @@ _fdt_reloc_done: /* Wait for boot hart */ _wait_for_boot_hart: + fence rw, rw la a4, _boot_hart_done REG_L a5, (a4) beqz a5, _wait_for_boot_hart |