diff options
| author | Atish Patra <atish.patra@wdc.com> | 2021-11-08 10:53:04 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-11-11 17:52:19 +0530 |
| commit | b628cfd6a0c1e8bf858b33a62d6a6fa16f4db640 (patch) | |
| tree | ba253574b6394683f4bc87fc88cfbad3f2bd4cec | |
| parent | 1e147324f0f82a9982b65b1fa2e97e6b5d5e57fe (diff) | |
lib: sbi: Counter info width should be zero indexed
The mhpm bits represent the number of bits available in mhpmcounter
while counter width describes a zero indexed value. Fix the counter width
calculation.
Fixes: 13d40f21d588 ("lib: sbi: Add PMU support")
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
| -rw-r--r-- | lib/sbi/sbi_pmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 1bb3e49..da8a37b 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -649,7 +649,7 @@ int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info) if (cidx == 0 || cidx == 2) cinfo.width = 63; else - cinfo.width = sbi_hart_mhpm_bits(scratch); + cinfo.width = sbi_hart_mhpm_bits(scratch) - 1; } else { /* it's a firmware counter */ cinfo.type = SBI_PMU_CTR_TYPE_FW; |