diff options
| author | Atish Patra <atish.patra@wdc.com> | 2021-11-08 10:53:03 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-11-11 17:50:32 +0530 |
| commit | 1e147324f0f82a9982b65b1fa2e97e6b5d5e57fe (patch) | |
| tree | 1644b54b20f0b03b7b01dfc0aec88aacee46527a | |
| parent | 0c304b661965d81ba2194b54a0c71f4c2e5cab16 (diff) | |
lib: sbi: Reset the mhpmevent value upon counter reset
The hardware solely relies on the event selector value in mhpmevent
to figure out what event to monitor using that counter. It should be
reset when counter reset happens.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
| -rw-r--r-- | lib/sbi/sbi_pmu.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 818b875..1bb3e49 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -369,6 +369,20 @@ static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t fw_evt_code) return 0; } +static int pmu_reset_hw_mhpmevent(int ctr_idx) +{ + if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX) + return SBI_EFAIL; +#if __riscv_xlen == 32 + csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0); + csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, 0); +#else + csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, 0); +#endif + + return 0; +} + int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, unsigned long flag) { @@ -392,8 +406,10 @@ int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, else ret = pmu_ctr_stop_hw(cbase); - if (!ret && (flag & SBI_PMU_STOP_FLAG_RESET)) + if (flag & SBI_PMU_STOP_FLAG_RESET) { active_events[hartid][cbase] = SBI_PMU_EVENT_IDX_INVALID; + pmu_reset_hw_mhpmevent(cbase); + } } return ret; |