diff options
| author | Atish Patra <atish.patra@wdc.com> | 2021-11-08 10:52:57 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-11-11 17:39:38 +0530 |
| commit | 7084ad9f4281eecd7a7f66cecfd7d9cff8d452ad (patch) | |
| tree | c2b2150c773d7a5919196cd4812606893b47ccc4 | |
| parent | a74daf2cb982269eb9cda5a71eef27c0f869ea08 (diff) | |
lib: sbi: Update csr_read/write_num for PMU
The Sscofpmf extension introduces mhpmevent[h] csrs to handle filtering
/overflow bits in RV32. There is no way to read/write mcountinhibit
using mcountinhibit csr using a variable.
Updated the support to read/write mhpmevent[h] and mcountinhibit csr.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
| -rw-r--r-- | lib/sbi/riscv_asm.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index f6b8c8e..25b40cf 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -126,6 +126,11 @@ unsigned long csr_read_num(int csr_num) switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret) switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret) switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret) + switchcase_csr_read(CSR_MCOUNTINHIBIT, ret) + switchcase_csr_read(CSR_MHPMEVENT3, ret) + switchcase_csr_read_4(CSR_MHPMEVENT4, ret) + switchcase_csr_read_8(CSR_MHPMEVENT8, ret) + switchcase_csr_read_16(CSR_MHPMEVENT16, ret) #if __riscv_xlen == 32 switchcase_csr_read(CSR_MCYCLEH, ret) switchcase_csr_read(CSR_MINSTRETH, ret) @@ -133,6 +138,10 @@ unsigned long csr_read_num(int csr_num) switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret) switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret) switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret) + switchcase_csr_read(CSR_MHPMEVENT3H, ret) + switchcase_csr_read_4(CSR_MHPMEVENT4H, ret) + switchcase_csr_read_8(CSR_MHPMEVENT8H, ret) + switchcase_csr_read_16(CSR_MHPMEVENT16H, ret) #endif default: @@ -192,6 +201,10 @@ void csr_write_num(int csr_num, unsigned long val) switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val) switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val) switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val) + switchcase_csr_write(CSR_MHPMEVENT3H, val) + switchcase_csr_write_4(CSR_MHPMEVENT4H, val) + switchcase_csr_write_8(CSR_MHPMEVENT8H, val) + switchcase_csr_write_16(CSR_MHPMEVENT16H, val) #endif switchcase_csr_write(CSR_MCOUNTINHIBIT, val) switchcase_csr_write(CSR_MHPMEVENT3, val) |