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Diffstat (limited to 'lib/sbi/riscv_asm.c')
-rw-r--r--lib/sbi/riscv_asm.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c
index f6b8c8e..25b40cf 100644
--- a/lib/sbi/riscv_asm.c
+++ b/lib/sbi/riscv_asm.c
@@ -126,6 +126,11 @@ unsigned long csr_read_num(int csr_num)
switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret)
switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret)
switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret)
+ switchcase_csr_read(CSR_MCOUNTINHIBIT, ret)
+ switchcase_csr_read(CSR_MHPMEVENT3, ret)
+ switchcase_csr_read_4(CSR_MHPMEVENT4, ret)
+ switchcase_csr_read_8(CSR_MHPMEVENT8, ret)
+ switchcase_csr_read_16(CSR_MHPMEVENT16, ret)
#if __riscv_xlen == 32
switchcase_csr_read(CSR_MCYCLEH, ret)
switchcase_csr_read(CSR_MINSTRETH, ret)
@@ -133,6 +138,10 @@ unsigned long csr_read_num(int csr_num)
switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret)
switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret)
switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret)
+ switchcase_csr_read(CSR_MHPMEVENT3H, ret)
+ switchcase_csr_read_4(CSR_MHPMEVENT4H, ret)
+ switchcase_csr_read_8(CSR_MHPMEVENT8H, ret)
+ switchcase_csr_read_16(CSR_MHPMEVENT16H, ret)
#endif
default:
@@ -192,6 +201,10 @@ void csr_write_num(int csr_num, unsigned long val)
switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val)
switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val)
switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val)
+ switchcase_csr_write(CSR_MHPMEVENT3H, val)
+ switchcase_csr_write_4(CSR_MHPMEVENT4H, val)
+ switchcase_csr_write_8(CSR_MHPMEVENT8H, val)
+ switchcase_csr_write_16(CSR_MHPMEVENT16H, val)
#endif
switchcase_csr_write(CSR_MCOUNTINHIBIT, val)
switchcase_csr_write(CSR_MHPMEVENT3, val)