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2023-07-17riscv: dts: starfive: increase the size of the SPL partitionHEADjh7110-6.4.yAurelien Jarno
Increase the size of the SPL partition from 0x20000 to 0x40000 to match the vendor kernel and support newer firmware version. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02[HACK] riscv: dts: starfive: Add VisionFive 2 reserved memory nodeEmil Renner Berthing
Add reserving memory node to the StarFive VisionFive 2 device tree telling linux to avoid memory used by OpenSBI. This avoids an error when booting through their U-Boots EFI implementation. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoCWilliam Qiu
Add the quad spi controller node for the StarFive JH7110 SoC. Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230619083517.415597-4-william.qiu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPIWilliam Qiu
Add QSPI clock operation in device probe. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202306022017.UbwjjWRN-lkp@intel.com/ Reported-by: Julia Lawall <julia.lawall@inria.fr> Closes: https://lore.kernel.org/r/202306040644.6ZHs55x4-lkp@intel.com/ Link: https://lore.kernel.org/r/20230619083517.415597-3-william.qiu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoCWilliam Qiu
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230619083517.415597-2-william.qiu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02riscv: dts: starfive: add PCIe dts configuration for JH7110Minda Chen
The PCIe is a PCIe2, single lane PCIe compliant controller. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Link: https://lore.kernel.org/r/20230406111142.74410-4-minda.chen@starfivetech.com Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02pcie: starfive: add StarFive JH7110 PCIe driver.Minda Chen
Add PCIe controller driver for StarFive JH7110 SoC platform. The PCIe controller is PCIe 2.0, single lane. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Link: https://lore.kernel.org/r/20230406111142.74410-3-minda.chen@starfivetech.com Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02dt-binding: pci: add JH7110 PCIe dt-binding documents.Minda Chen
Add PCIe controller driver dt-binding documents for StarFive JH7110 SoC platform. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Link: https://lore.kernel.org/r/20230406111142.74410-2-minda.chen@starfivetech.com Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02riscv: dts: starfive: Add USB dts configuration for JH7110Minda Chen
Add USB wrapper layer and Cadence USB3 controller dts configuration for StarFive JH7110 SoC and VisionFive2 Board. USB controller connect to PHY, The PHY dts configuration are also added. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Link: https://lore.kernel.org/r/20230518112750.57924-8-minda.chen@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02phy: starfive: Add JH7110 PCIE 2.0 PHY driverMinda Chen
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-5-minda.chen@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02phy: starfive: Add JH7110 USB 2.0 PHY driverMinda Chen
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-4-minda.chen@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: phy: Add StarFive JH7110 PCIe PHYMinda Chen
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-3-minda.chen@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: phy: Add StarFive JH7110 USB PHYMinda Chen
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-2-minda.chen@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02riscv: dts: starfive: add dma controller nodeWalker Chen
Add the dma controller node for the Starfive JH7110 SoC. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Link: https://lore.kernel.org/r/20230322094820.24738-5-walker.chen@starfivetech.com [esmil: resolve context] Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02riscv: dts: starfive: Add TRNG node for VisionFive 2Jia Jie Ho
Adding StarFive TRNG controller node to VisionFive 2 SoC. Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230117015445.32500-4-jiajie.ho@starfivetech.com [esmil: resolve context and update clock/reset names] Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02riscv: dts: starfive: jh7110: Add temperature sensorEmil Renner Berthing
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02riscv: dts: starfive: visionfive 2: Add configuration of gmac and phySamin Guo
v1.3B: v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and inverse configurations. The tx_clk of v1.3B uses an external clock and needs to be switched to an external clock source. v1.2A: v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay configurations. v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and rx to external clock sources. Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Link: https://lore.kernel.org/r/20230313034645.5469-9-samin.guo@starfivetech.com Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02riscv: dts: starfive: jh7110: Add ethernet device nodesSamin Guo
Add JH7110 ethernet device node to support gmac driver for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Link: https://lore.kernel.org/r/20230313034645.5469-8-samin.guo@starfivetech.com [esmil: fix context and move stmmac-axi-config after external clocks] Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02riscv: dts: starfive: Add mmc nodeWilliam Qiu
Add the mmc node for the StarFive JH7110 SoC. Set mmco node to emmc and set mmc1 node to sd. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Link: https://lore.kernel.org/r/20230215113249.47727-4-william.qiu@starfivetech.com [esmil: add only mmc nodes and sort by address] Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-07-02riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodesXingyu Wu
Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110 System-Top-Group, Image-Signal-Process and Video-Output clock and reset drivers for the JH7110 RISC-V SoC. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-12-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocksXingyu Wu
Add DVP and HDMI TX pixel external fixed clocks and the rates are 74.25MHz and 297MHz. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-11-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets supportXingyu Wu
Add new struct members and auxiliary_device_id of resets to support System-Top-Group, Image-Signal-Process and Video-Output on the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-9-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02MAINTAINERS: Update maintainer of JH71x0 clock driversXingyu Wu
Add a new maintainer which is in charge of StarFive JH7110 STG/ISP/VOUT clock drivers. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-8-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02clk: starfive: Add StarFive JH7110 Video-Output clock driverXingyu Wu
Add driver for the StarFive JH7110 Video-Output clock controller. And these clock controllers should power on and enable the clocks from SYSCRG first before registering. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-7-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generatorXingyu Wu
Add bindings for the Video-Output clock and reset generator (VOUTCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-6-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driverXingyu Wu
Add driver for the StarFive JH7110 Image-Signal-Process clock controller. And these clock controllers should power on and enable the clocks from SYSCRG first before registering. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-5-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset ↵Xingyu Wu
generator Add bindings for the Image-Signal-Process clock and reset generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-4-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02clk: starfive: Add StarFive JH7110 System-Top-Group clock driverEmil Renner Berthing
Add driver for the StarFive JH7110 System-Top-Group clock controller. Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Link: https://lore.kernel.org/r/20230518101234.143748-3-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset ↵Xingyu Wu
generator Add bindings for the System-Top-Group clock and reset generator (STGCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230518101234.143748-2-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02riscv: dts: starfive: jh7110: Add PLL clock source in SYSCRG nodeXingyu Wu
Modify the SYSCRG node to add PLL clocks input from PLL clocks driver. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230613125852.211636-8-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02riscv: dts: starfive: jh7110: Add syscon nodesWilliam Qiu
Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 Soc. Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Link: https://lore.kernel.org/r/20230613125852.211636-7-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02clk: starfive: jh7110-sys: Add PLL clocks source from DTSXingyu Wu
Modify PLL clocks source to be got from DTS or the fixed factor clocks. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230613125852.211636-6-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02clk: starfive: Add StarFive JH7110 PLL clock driverXingyu Wu
Add driver for the StarFive JH7110 PLL clock controller and they work by reading and setting syscon registers. Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230613125852.211636-5-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: clock: jh7110-syscrg: Add PLL clock inputsXingyu Wu
Add optional PLL clock inputs from PLL clock generator. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230613125852.211636-4-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: soc: starfive: Add StarFive syscon moduleWilliam Qiu
Add documentation to describe StarFive System Controller Registers. Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Link: https://lore.kernel.org/r/20230613125852.211636-3-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02dt-bindings: clock: Add StarFive JH7110 PLL clock generatorXingyu Wu
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230613125852.211636-2-xingyu.wu@starfivetech.com Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2023-07-02usb: cdns3: Add StarFive JH7110 USB driverMinda Chen
Adds Specific Glue layer to support USB peripherals on StarFive JH7110 SoC. There is a Cadence USB3 core for JH7110 SoCs, the cdns core is the child of this USB wrapper module device. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Peter Chen <peter.chen@kernel.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230518112750.57924-7-minda.chen@starfivetech.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit bfb46b424652a3396b92ca3c96c169ade9b45b8d)
2023-07-02dt-bindings: usb: Add StarFive JH7110 USB controllerMinda Chen
StarFive JH7110 platforms USB have a wrapper module around the Cadence USBSS-DRD controller. Add binding information doc for that. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Peter Chen <peter.chen@kernel.org> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230518112750.57924-6-minda.chen@starfivetech.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 5aa735a4742c5ffff2fe34f764cbcbd917e100ae)
2023-07-02riscv: dts: starfive: jh7110: Add watchdog nodeXingyu Wu
Add the watchdog node for the Starfive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> (cherry picked from commit 6361b7de262aca8704abfaade5166a940f7cc571)
2023-07-02riscv: dts: starfive: jh7100: Add watchdog nodeXingyu Wu
Add watchdog node for the StarFive JH7100 RISC-V SoC. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> (cherry picked from commit 435ac3fbfbc64a4557862a612058383748a3c7f0)
2023-07-02riscv: dts: starfive: Add PMU controller nodeWalker Chen
Add the pmu controller node for the StarFive JH7110 SoC. The PMU needs to be used by other modules, e.g. VPU,ISP,etc. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> (cherry picked from commit 6a887bcc4138de9747fdfafc4ebf0a1c6ef4b2c1)
2023-07-01Linux 6.4.1v6.4.1Greg Kroah-Hartman
Link: https://lore.kernel.org/r/20230629184151.888604958@linuxfoundation.org Tested-by: Ronald Warsow <rwarsow@gmx.de> Link: https://lore.kernel.org/r/20230630055626.202608973@linuxfoundation.org Link: https://lore.kernel.org/r/20230630072101.040486316@linuxfoundation.org Tested-by: Ron Economos <re@w6rz.net> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Rudi Heitbaum <rudi@heitbaum.com> Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-01xtensa: fix NOMMU build with lock_mm_and_find_vma() conversionLinus Torvalds
commit d85a143b69abb4d7544227e26d12c4c7735ab27d upstream. It turns out that xtensa has a really odd configuration situation: you can do a no-MMU config, but still have the page fault code enabled. Which doesn't sound all that sensible, but it turns out that xtensa can have protection faults even without the MMU, and we have this: config PFAULT bool "Handle protection faults" if EXPERT && !MMU default y help Handle protection faults. MMU configurations must enable it. noMMU configurations may disable it if used memory map never generates protection faults or faults are always fatal. If unsure, say Y. which completely violated my expectations of the page fault handling. End result: Guenter reports that the xtensa no-MMU builds all fail with arch/xtensa/mm/fault.c: In function ‘do_page_fault’: arch/xtensa/mm/fault.c:133:8: error: implicit declaration of function ‘lock_mm_and_find_vma’ because I never exposed the new lock_mm_and_find_vma() function for the no-MMU case. Doing so is simple enough, and fixes the problem. Reported-and-tested-by: Guenter Roeck <linux@roeck-us.net> Fixes: a050ba1e7422 ("mm/fault: convert remaining simple cases to lock_mm_and_find_vma()") Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-01csky: fix up lock_mm_and_find_vma() conversionLinus Torvalds
commit e55e5df193d247a38a5e1ac65a5316a0adcc22fa upstream. As already mentioned in my merge message for the 'expand-stack' branch, we have something like 24 different versions of the page fault path for all our different architectures, all just _slightly_ different due to various historical reasons (usually related to exactly when they branched off the original i386 version, and the details of the other architectures they had in their history). And a few of them had some silly mistake in the conversion. Most of the architectures call the faulting address 'address' in the fault path. But not all. Some just call it 'addr'. And if you end up doing a bit too much copy-and-paste, you end up with the wrong version in the places that do it differently. In this case it was csky. Fixes: a050ba1e7422 ("mm/fault: convert remaining simple cases to lock_mm_and_find_vma()") Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-01parisc: fix expand_stack() conversionLinus Torvalds
commit ea3f8272876f2958463992f6736ab690fde7fa9c upstream. In commit 8d7071af8907 ("mm: always expand the stack with the mmap write lock held") I tried to deal with the remaining odd page fault handling cases. The oddest one is ia64, which has stacks that grow both up and down. And because ia64 was _so_ odd, I asked people to verify the end result. But a close second oddity is parisc, which is the only one that has a main stack growing up (our "CONFIG_STACK_GROWSUP" config option). But it looked obvious enough that I didn't worry about it. I should have worried a bit more. Not because it was particularly complex, but because I just used the wrong variable name. The previous vma isn't called "prev", it's called "prev_vma". Blush. Fixes: 8d7071af8907 ("mm: always expand the stack with the mmap write lock held") Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-01sparc32: fix lock_mm_and_find_vma() conversionLinus Torvalds
commit 0b26eadbf200abf6c97c6d870286c73219cdac65 upstream. The sparc32 conversion to lock_mm_and_find_vma() in commit a050ba1e7422 ("mm/fault: convert remaining simple cases to lock_mm_and_find_vma()") missed the fact that we didn't actually have a 'regs' pointer available in the 'force_user_fault()' case. It's there in the regular page fault path ("do_sparc_fault()"), but not the window underflow/overflow paths. Which is all fine - we can just pass in a NULL pointer. The register state is only used to avoid deadlock with kernel faults, which is not the case for any of these register window faults. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: a050ba1e7422 ("mm/fault: convert remaining simple cases to lock_mm_and_find_vma()") Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-01Revert "thermal/drivers/mediatek: Use devm_of_iomap to avoid resource leak ↵Ricardo Cañuelo
in mtk_thermal_probe" commit 86edac7d3888c715fe3a81bd61f3617ecfe2e1dd upstream. This reverts commit f05c7b7d9ea9477fcc388476c6f4ade8c66d2d26. That change was causing a regression in the generic-adc-thermal-probed bootrr test as reported in the kernelci-results list [1]. A proper rework will take longer, so revert it for now. [1] https://groups.io/g/kernelci-results/message/42660 Fixes: f05c7b7d9ea9 ("thermal/drivers/mediatek: Use devm_of_iomap to avoid resource leak in mtk_thermal_probe") Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com> Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230525121811.3360268-1-ricardo.canuelo@collabora.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-01HID: logitech-hidpp: add HIDPP_QUIRK_DELAYED_INIT for the T651.Mike Hommey
commit 5fe251112646d8626818ea90f7af325bab243efa upstream. commit 498ba2069035 ("HID: logitech-hidpp: Don't restart communication if not necessary") put restarting communication behind that flag, and this was apparently necessary on the T651, but the flag was not set for it. Fixes: 498ba2069035 ("HID: logitech-hidpp: Don't restart communication if not necessary") Cc: stable@vger.kernel.org Signed-off-by: Mike Hommey <mh@glandium.org> Link: https://lore.kernel.org/r/20230617230957.6mx73th4blv7owqk@glandium.org Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-01HID: hidraw: fix data race on device refcountLudvig Michaelsson
commit 944ee77dc6ec7b0afd8ec70ffc418b238c92f12b upstream. The hidraw_open() function increments the hidraw device reference counter. The counter has no dedicated synchronization mechanism, resulting in a potential data race when concurrently opening a device. The race is a regression introduced by commit 8590222e4b02 ("HID: hidraw: Replace hidraw device table mutex with a rwsem"). While minors_rwsem is intended to protect the hidraw_table itself, by instead acquiring the lock for writing, the reference counter is also protected. This is symmetrical to hidraw_release(). Link: https://github.com/systemd/systemd/issues/27947 Fixes: 8590222e4b02 ("HID: hidraw: Replace hidraw device table mutex with a rwsem") Cc: stable@vger.kernel.org Signed-off-by: Ludvig Michaelsson <ludvig.michaelsson@yubico.com> Link: https://lore.kernel.org/r/20230621-hidraw-race-v1-1-a58e6ac69bab@yubico.com Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-01fbdev: fix potential OOB read in fast_imageblit()Zhang Shurong
commit c2d22806aecb24e2de55c30a06e5d6eb297d161d upstream. There is a potential OOB read at fast_imageblit, for "colortab[(*src >> 4)]" can become a negative value due to "const char *s = image->data, *src". This change makes sure the index for colortab always positive or zero. Similar commit: https://patchwork.kernel.org/patch/11746067 Potential bug report: https://groups.google.com/g/syzkaller-bugs/c/9ubBXKeKXf4/m/k-QXy4UgAAAJ Signed-off-by: Zhang Shurong <zhang_shurong@foxmail.com> Cc: stable@vger.kernel.org Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.2.3 (git 2.25.1) at 2023-09-25 17:17:35 +0000