diff options
| author | NIIBE Yutaka <gniibe@fsij.org> | 2016-06-29 16:37:09 +0900 |
|---|---|---|
| committer | NIIBE Yutaka <gniibe@fsij.org> | 2016-06-29 16:38:18 +0900 |
| commit | 41ac81a66bc48ff4d34bc5013630f90d4fa561f5 (patch) | |
| tree | f7d7d8b9a7282b460b492dc95cba684ba399c26e /mcu | |
| parent | 986518fba746fe50c98597665d1c4d349b631c1b (diff) | |
Update example for fs-bb48
Diffstat (limited to 'mcu')
| -rw-r--r-- | mcu/clk_gpio_init-mkl27z.c | 44 | ||||
| -rw-r--r-- | mcu/mkl27z.h | 38 |
2 files changed, 42 insertions, 40 deletions
diff --git a/mcu/clk_gpio_init-mkl27z.c b/mcu/clk_gpio_init-mkl27z.c index 4040136..894a8ad 100644 --- a/mcu/clk_gpio_init-mkl27z.c +++ b/mcu/clk_gpio_init-mkl27z.c @@ -66,10 +66,12 @@ clock_init (void) while ((MCG->S & 0x0c) != 0) ; - SIM->SOPT2 = 0x00040060; /* USBSRC=IRC48, CLOKOUTSEL=LPO, RTC-clock */ + /* TPMSRC=IRC48M, USBSRC=IRC48M, CLOKOUTSEL=LPO, RTC-clock */ + SIM->SOPT2 = 0x01040060; - SIM->SCGC4 = (1 << 18); /* Enable USB FS clock */ + SIM->SCGC4 = (1 << 18); /* Enable USB FS clock */ SIM->SCGC5 = (1 << 10); /* Enable Port B clock */ + SIM->SCGC6 = (1 << 25); /* Enable TPM1 clock */ SIM->COPC = 0; /* COP disabled */ /* Crystal-less USB setup. */ @@ -78,44 +80,6 @@ clock_init (void) } -struct PORT { - volatile uint32_t PCR0; volatile uint32_t PCR1; - volatile uint32_t PCR2; volatile uint32_t PCR3; - volatile uint32_t PCR4; volatile uint32_t PCR5; - volatile uint32_t PCR6; volatile uint32_t PCR7; - volatile uint32_t PCR8; volatile uint32_t PCR9; - volatile uint32_t PCR10; volatile uint32_t PCR11; - volatile uint32_t PCR12; volatile uint32_t PCR13; - volatile uint32_t PCR14; volatile uint32_t PCR15; - volatile uint32_t PCR16; volatile uint32_t PCR17; - volatile uint32_t PCR18; volatile uint32_t PCR19; - volatile uint32_t PCR20; volatile uint32_t PCR21; - volatile uint32_t PCR22; volatile uint32_t PCR23; - volatile uint32_t PCR24; volatile uint32_t PCR25; - volatile uint32_t PCR26; volatile uint32_t PCR27; - volatile uint32_t PCR28; volatile uint32_t PCR29; - volatile uint32_t PCR30; volatile uint32_t PCR31; - volatile uint32_t GPCLR; volatile uint32_t GPCHR; - uint32_t reserved[6]; - volatile uint32_t ISFR; -}; -static struct PORT *const PORTB = (struct PORT *const)0x4004A000; -static struct PORT *const PORTD = (struct PORT *const)0x4004C000; -static struct PORT *const PORTE = (struct PORT *const)0x4004D000; - -struct GPIO { - volatile uint32_t PDOR; /* Port Data Output Register */ - volatile uint32_t PSOR; /* Port Set Output Register */ - volatile uint32_t PCOR; /* Port Clear Output Register */ - volatile uint32_t PTOR; /* Port Toggle Output Register */ - volatile uint32_t PDIR; /* Port Data Input Register */ - volatile uint32_t PDDR; /* Port Data Direction Register */ -}; -static struct GPIO *const GPIOB = (struct GPIO *const)0x400FF040; -static struct GPIO *const GPIOD = (struct GPIO *const)0x400FF0C0; -static struct GPIO *const GPIOE = (struct GPIO *const)0x400FF100; - - static void __attribute__((used)) gpio_init (void) { diff --git a/mcu/mkl27z.h b/mcu/mkl27z.h index 368ef30..ad3c54c 100644 --- a/mcu/mkl27z.h +++ b/mcu/mkl27z.h @@ -29,3 +29,41 @@ struct SIM { volatile uint32_t SRVCOP; /* Service COP */ }; static struct SIM *const SIM = (struct SIM *const)0x40047000; + +/* Port control. */ +struct PORT { + volatile uint32_t PCR0; volatile uint32_t PCR1; + volatile uint32_t PCR2; volatile uint32_t PCR3; + volatile uint32_t PCR4; volatile uint32_t PCR5; + volatile uint32_t PCR6; volatile uint32_t PCR7; + volatile uint32_t PCR8; volatile uint32_t PCR9; + volatile uint32_t PCR10; volatile uint32_t PCR11; + volatile uint32_t PCR12; volatile uint32_t PCR13; + volatile uint32_t PCR14; volatile uint32_t PCR15; + volatile uint32_t PCR16; volatile uint32_t PCR17; + volatile uint32_t PCR18; volatile uint32_t PCR19; + volatile uint32_t PCR20; volatile uint32_t PCR21; + volatile uint32_t PCR22; volatile uint32_t PCR23; + volatile uint32_t PCR24; volatile uint32_t PCR25; + volatile uint32_t PCR26; volatile uint32_t PCR27; + volatile uint32_t PCR28; volatile uint32_t PCR29; + volatile uint32_t PCR30; volatile uint32_t PCR31; + volatile uint32_t GPCLR; volatile uint32_t GPCHR; + uint32_t reserved[6]; + volatile uint32_t ISFR; +}; +static struct PORT *const PORTB = (struct PORT *const)0x4004A000; +static struct PORT *const PORTD = (struct PORT *const)0x4004C000; +static struct PORT *const PORTE = (struct PORT *const)0x4004D000; + +struct GPIO { + volatile uint32_t PDOR; /* Port Data Output Register */ + volatile uint32_t PSOR; /* Port Set Output Register */ + volatile uint32_t PCOR; /* Port Clear Output Register */ + volatile uint32_t PTOR; /* Port Toggle Output Register */ + volatile uint32_t PDIR; /* Port Data Input Register */ + volatile uint32_t PDDR; /* Port Data Direction Register */ +}; +static struct GPIO *const GPIOB = (struct GPIO *const)0x400FF040; +static struct GPIO *const GPIOD = (struct GPIO *const)0x400FF0C0; +static struct GPIO *const GPIOE = (struct GPIO *const)0x400FF100; |