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authorNIIBE Yutaka <gniibe@fsij.org>2016-06-02 11:01:11 +0900
committerNIIBE Yutaka <gniibe@fsij.org>2016-06-02 11:01:11 +0900
commit78718e57df6f55c0670cdb6b70337204dd045dba (patch)
tree1e7a70e70931a0fdf65b04dd447e473c5e846bc7 /contrib
parenta756987d2ae2a029bfe5c8cf00a9853379fbcb91 (diff)
Move files
Diffstat (limited to 'contrib')
-rw-r--r--contrib/adc-mkl27z.c320
-rw-r--r--contrib/adc-stm32f103.c328
2 files changed, 648 insertions, 0 deletions
diff --git a/contrib/adc-mkl27z.c b/contrib/adc-mkl27z.c
new file mode 100644
index 0000000..19f9f5b
--- /dev/null
+++ b/contrib/adc-mkl27z.c
@@ -0,0 +1,320 @@
+/*
+ * adc-mkl27z.c - ADC driver for MKL27Z
+ * In this ADC driver, there are NeuG specific parts.
+ * It only records lower 8-bit of 16-bit data.
+ * You need to modify to use this as generic ADC driver.
+ *
+ * Copyright (C) 2016 Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <mcu/mkl27z.h>
+
+struct DMAMUX {
+ volatile uint32_t CHCFG0;
+ volatile uint32_t CHCFG1;
+ volatile uint32_t CHCFG2;
+ volatile uint32_t CHCFG3;
+};
+static struct DMAMUX *const DMAMUX = (struct DMAMUX *const)0x40021000;
+
+#define INTR_REQ_DMA0 0
+
+struct DMA {
+ volatile uint32_t SAR;
+ volatile uint32_t DAR;
+ volatile uint32_t DSR_BCR;
+ volatile uint32_t DCR;
+};
+static struct DMA *const DMA0 = (struct DMA *const)0x40008100;
+static struct DMA *const DMA1 = (struct DMA *const)0x40008110;
+
+
+/* We don't use ADC interrupt. Just for reference. */
+#define INTR_REQ_ADC 15
+
+struct ADC {
+ volatile uint32_t SC1[2];/* Status and Control Registers 1 */
+ volatile uint32_t CFG1; /* Configuration Register 1 */
+ volatile uint32_t CFG2; /* Configuration Register 2 */
+ volatile uint32_t R[2]; /* Data Result Register */
+
+ /* Compare Value Registers 1, 2 */
+ volatile uint32_t CV1;
+ volatile uint32_t CV2;
+
+ volatile uint32_t SC2; /* Status and Control Register 2 */
+ volatile uint32_t SC3; /* Status and Control Register 3 */
+
+ volatile uint32_t OFS; /* Offset Correction Register */
+ volatile uint32_t PG; /* Plus-Side Gain Register */
+ volatile uint32_t MG; /* Minus-Side Gain Register */
+
+ /* Plus-Side General Calibration Value Registers */
+ volatile uint32_t CLPD;
+ volatile uint32_t CLPS;
+ volatile uint32_t CLP4;
+ volatile uint32_t CLP3;
+ volatile uint32_t CLP2;
+ volatile uint32_t CLP1;
+ volatile uint32_t CLP0;
+ uint32_t rsvd0;
+ /* Minus-Side General Calibration Value Registers */
+ volatile uint32_t CLMD;
+ volatile uint32_t CLMS;
+ volatile uint32_t CLM4;
+ volatile uint32_t CLM3;
+ volatile uint32_t CLM2;
+ volatile uint32_t CLM1;
+ volatile uint32_t CLM0;
+};
+static struct ADC *const ADC0 = (struct ADC *const)0x4003B000;
+
+/* SC1 */
+#define ADC_SC1_DIFF (1 << 5)
+#define ADC_SC1_AIEN (1 << 6)
+#define ADC_SC1_COCO (1 << 7)
+#define ADC_SC1_TEMPSENSOR 26
+#define ADC_SC1_BANDGAP 27
+#define ADC_SC1_ADCSTOP 31
+
+/* CFG1 */
+#define ADC_CLOCK_SOURCE_ASYNCH (3 << 0)
+#define ADC_MODE_16BIT (3 << 2)
+#define ADC_ADLSMP_SHORT (0 << 4)
+#define ADC_ADLSMP_LONG (1 << 4)
+#define ADC_ADIV_1 (0 << 5)
+#define ADC_ADIV_8 (3 << 5)
+#define ADC_ADLPC_NORMAL (0 << 7)
+#define ADC_ADLPC_LOWPOWER (1 << 7)
+/**/
+#define ADC_CLOCK_SOURCE ADC_CLOCK_SOURCE_ASYNCH
+#define ADC_MODE ADC_MODE_16BIT
+#define ADC_ADLSMP ADC_ADLSMP_SHORT
+#define ADC_ADIV ADC_ADIV_1
+#define ADC_ADLPC ADC_ADLPC_LOWPOWER
+
+/* CFG2 */
+#define ADC_ADLSTS_DEFAULT 0 /* 24 cycles if CFG1.ADLSMP=1, 4 if not. */
+#define ADC_ADHSC_NORMAL (0 << 2)
+#define ADC_ADHSC_HIGHSPEED (1 << 2)
+#define ADC_ADACK_DISABLE (0 << 3)
+#define ADC_ADACK_ENABLE (1 << 3)
+#define ADC_MUXSEL_A (0 << 4)
+#define ADC_MUXSEL_B (1 << 4)
+/**/
+#define ADC_ADLSTS ADC_ADLSTS_DEFAULT
+#define ADC_ADHSC ADC_ADHSC_NORMAL
+#define ADC_ADACKEN ADC_ADACK_ENABLE
+#define ADC_MUXSEL ADC_MUXSEL_A
+
+/* SC2 */
+#define ADC_SC2_REFSEL_DEFAULT 1 /* Internal Voltage Reference??? */
+#define ADC_SC2_DMAEN (1 << 2)
+#define ADC_SC2_ACREN (1 << 3)
+#define ADC_SC2_ACFGT (1 << 4)
+#define ADC_SC2_ACFE (1 << 5)
+#define ADC_SC2_ADTRG (1 << 6) /* For hardware trigger */
+
+/* SC3 */
+#define ADC_SC3_AVGS11 0x03
+#define ADC_SC3_AVGE (1 << 2)
+#define ADC_SC3_ADCO (1 << 3)
+#define ADC_SC3_CALF (1 << 6)
+#define ADC_SC3_CAL (1 << 7)
+
+#define ADC_DMA_SLOT_NUM 40
+
+/*
+ * Buffer to save ADC data.
+ */
+uint32_t adc_buf[64];
+
+static const uint32_t adc0_sc1_setting = ADC_SC1_TEMPSENSOR;
+
+static chopstx_intr_t adc_intr;
+
+struct adc_internal {
+ uint32_t buf[64];
+ uint8_t *p;
+ int phase : 8;
+ int count : 8;
+};
+struct adc_internal adc;
+
+/*
+ * Initialize ADC module, do calibration.
+ *
+ * This is called by MAIN, only once, hopefully before creating any
+ * other threads (to be accurate).
+ *
+ * We configure ADC0 to kick DMA0, configure DMA0 to kick DMA1.
+ * DMA0 records output of ADC0 to the ADC.BUF.
+ * DMA1 kicks ADC0 again to get another value.
+ *
+ * ADC0 --[finish conversion]--> DMA0 --[Link channel 1]--> DMA1
+ */
+int
+adc_init (void)
+{
+ uint32_t v;
+
+ /* Enable ADC0 and DMAMUX clock. */
+ SIM->SCGC6 |= (1 << 27) | (1 << 1);
+ /* Enable DMA clock. */
+ SIM->SCGC7 |= (1 << 8);
+
+ /* ADC0 setting for calibration. */
+ ADC0->CFG1 = ADC_CLOCK_SOURCE | ADC_MODE | ADC_ADLSMP | ADC_ADIV | ADC_ADLPC;
+ ADC0->CFG2 = ADC_ADLSTS | ADC_ADHSC | ADC_ADACKEN | ADC_MUXSEL;
+ ADC0->SC2 = ADC_SC2_REFSEL_DEFAULT;
+ ADC0->SC3 = ADC_SC3_CAL | ADC_SC3_CALF | ADC_SC3_AVGE | ADC_SC3_AVGS11;
+
+ /* Wait ADC completion */
+ while ((ADC0->SC1[0] & ADC_SC1_COCO) == 0)
+ if ((ADC0->SC3 & ADC_SC3_CALF) != 0)
+ /* Calibration failure */
+ return -1;
+
+ if ((ADC0->SC3 & ADC_SC3_CALF) != 0)
+ /* Calibration failure */
+ return -1;
+
+ /* Configure PG by the calibration values. */
+ v = ADC0->CLP0 + ADC0->CLP1 + ADC0->CLP2 + ADC0->CLP3 + ADC0->CLP4 + ADC0->CLPS;
+ ADC0->PG = 0x8000 | (v >> 1);
+
+ /* Configure MG by the calibration values. */
+ v = ADC0->CLM0 + ADC0->CLM1 + ADC0->CLM2 + ADC0->CLM3 + ADC0->CLM4 + ADC0->CLMS;
+ ADC0->MG = 0x8000 | (v >> 1);
+
+ ADC0->SC1[0] = ADC_SC1_ADCSTOP;
+
+ /* DMAMUX setting. */
+ DMAMUX->CHCFG0 = (1 << 7) | ADC_DMA_SLOT_NUM;
+
+ /* DMA0 initial setting. */
+ DMA0->SAR = (uint32_t)&ADC0->R[0];
+
+ /* DMA1 initial setting. */
+ DMA1->SAR = (uint32_t)&adc0_sc1_setting;
+ DMA1->DAR = (uint32_t)&ADC0->SC1[0];
+
+ chopstx_claim_irq (&adc_intr, INTR_REQ_DMA0);
+ return 0;
+}
+
+/*
+ * Start using ADC.
+ */
+void
+adc_start (void)
+{
+ ADC0->CFG1 = ADC_CLOCK_SOURCE | ADC_MODE | ADC_ADLSMP | ADC_ADIV | ADC_ADLPC;
+ ADC0->CFG2 = ADC_ADLSTS | ADC_ADHSC | ADC_ADACKEN | ADC_MUXSEL;
+ ADC0->SC2 = ADC_SC2_REFSEL_DEFAULT | ADC_SC2_DMAEN;
+ ADC0->SC3 = 0;
+}
+
+/*
+ * Kick getting data for COUNT times.
+ * Data will be saved in ADC_BUF starting at OFFSET.
+ */
+static void
+adc_start_conversion_internal (int count)
+{
+ /* DMA0 setting. */
+ DMA0->DAR = (uint32_t)&adc.buf[0];
+ DMA0->DSR_BCR = 4 * count;
+ DMA0->DCR = (1 << 31) | (1 << 30) | (1 << 29) | (0 << 20) | (1 << 19)
+ | (0 << 17) | (1 << 7) | (2 << 4) | (1 << 2);
+
+ /* Kick DMA1. */
+ DMA1->DSR_BCR = 4 * count;
+ DMA1->DCR = (1 << 30) | (1 << 29) | (0 << 19) | (0 << 17) | (1 << 16) | (1 << 7);
+}
+
+
+/*
+ * Kick getting data for COUNT times.
+ * Data will be saved in ADC_BUF starting at OFFSET.
+ */
+void
+adc_start_conversion (int offset, int count)
+{
+ adc.p = (uint8_t *)&adc_buf[offset];
+ adc.phase = 0;
+ adc.count = count;
+ adc_start_conversion_internal (count);
+}
+
+
+static void
+adc_stop_conversion (void)
+{
+ ADC0->SC1[0] = ADC_SC1_ADCSTOP;
+}
+
+/*
+ * Stop using ADC.
+ */
+void
+adc_stop (void)
+{
+ SIM->SCGC6 &= ~(1 << 27);
+}
+
+/*
+ * Return 0 on success.
+ * Return 1 on error.
+ */
+int
+adc_wait_completion (void)
+{
+ while (1)
+ {
+ int i;
+
+ /* Wait DMA completion */
+ chopstx_poll (NULL, 1, &adc_intr);
+
+ DMA0->DSR_BCR = (1 << 24);
+ DMA1->DSR_BCR = (1 << 24);
+
+ adc_stop_conversion ();
+
+ for (i = 0; i < adc.count; i++)
+ *adc.p++ = (uint8_t)adc.buf[i];
+
+ if (++adc.phase >= 4)
+ break;
+
+ adc_start_conversion_internal (adc.count);
+ }
+
+ return 0;
+}
diff --git a/contrib/adc-stm32f103.c b/contrib/adc-stm32f103.c
new file mode 100644
index 0000000..6a8076e
--- /dev/null
+++ b/contrib/adc-stm32f103.c
@@ -0,0 +1,328 @@
+/*
+ * adc_stm32f103.c - ADC driver for STM32F103
+ * In this ADC driver, there are NeuG specific parts.
+ * You need to modify to use this as generic ADC driver.
+ *
+ * Copyright (C) 2011, 2012, 2013, 2015, 2016
+ * Free Software Initiative of Japan
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <mcu/stm32f103.h>
+#include "adc.h"
+
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+
+#define ADC_SMPR1_SMP_VREF(n) ((n) << 21)
+#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18)
+
+#define ADC_SMPR1_SMP_AN10(n) ((n) << 0)
+#define ADC_SMPR1_SMP_AN11(n) ((n) << 3)
+
+#define ADC_SMPR2_SMP_AN0(n) ((n) << 0)
+#define ADC_SMPR2_SMP_AN1(n) ((n) << 3)
+#define ADC_SMPR2_SMP_AN2(n) ((n) << 6)
+#define ADC_SMPR2_SMP_AN9(n) ((n) << 27)
+
+#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
+
+#define ADC_SQR3_SQ1_N(n) ((n) << 0)
+#define ADC_SQR3_SQ2_N(n) ((n) << 5)
+#define ADC_SQR3_SQ3_N(n) ((n) << 10)
+#define ADC_SQR3_SQ4_N(n) ((n) << 15)
+
+#define ADC_SAMPLE_1P5 0
+
+#define ADC_CHANNEL_IN0 0
+#define ADC_CHANNEL_IN1 1
+#define ADC_CHANNEL_IN2 2
+#define ADC_CHANNEL_IN9 9
+#define ADC_CHANNEL_IN10 10
+#define ADC_CHANNEL_IN11 11
+#define ADC_CHANNEL_SENSOR 16
+#define ADC_CHANNEL_VREFINT 17
+
+#define DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
+#define DELIBARATELY_DO_IT_WRONG_START_STOP
+
+#ifdef DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
+#define ADC_SAMPLE_VREF ADC_SAMPLE_1P5
+#define ADC_SAMPLE_SENSOR ADC_SAMPLE_1P5
+#else
+#define ADC_SAMPLE_VREF ADC_SAMPLE_239P5
+#define ADC_SAMPLE_SENSOR ADC_SAMPLE_239P5
+#endif
+
+#define NEUG_DMA_CHANNEL STM32_DMA1_STREAM1
+#define NEUG_DMA_MODE \
+ ( STM32_DMA_CR_PL (STM32_ADC_ADC1_DMA_PRIORITY) \
+ | STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD \
+ | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE \
+ | STM32_DMA_CR_TEIE )
+
+#define NEUG_ADC_SETTING1_SMPR1 ADC_SMPR1_SMP_VREF(ADC_SAMPLE_VREF) \
+ | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_SENSOR)
+#define NEUG_ADC_SETTING1_SMPR2 0
+#define NEUG_ADC_SETTING1_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_VREFINT) \
+ | ADC_SQR3_SQ2_N(ADC_CHANNEL_SENSOR) \
+ | ADC_SQR3_SQ3_N(ADC_CHANNEL_SENSOR) \
+ | ADC_SQR3_SQ4_N(ADC_CHANNEL_VREFINT)
+#define NEUG_ADC_SETTING1_NUM_CHANNELS 4
+
+/*
+ * ADC finish interrupt
+ */
+#define INTR_REQ_DMA1_Channel1 11
+
+static chopstx_intr_t adc_intr;
+
+/*
+ * Do calibration for both of ADCs.
+ */
+int
+adc_init (void)
+{
+ RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
+ RCC->APB2RSTR = (RCC_APB2RSTR_ADC1RST | RCC_APB2RSTR_ADC2RST);
+ RCC->APB2RSTR = 0;
+
+ ADC1->CR1 = 0;
+ ADC1->CR2 = ADC_CR2_ADON;
+ ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+ while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
+ ;
+ ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+ while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
+ ;
+ ADC1->CR2 = 0;
+
+ ADC2->CR1 = 0;
+ ADC2->CR2 = ADC_CR2_ADON;
+ ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+ while ((ADC2->CR2 & ADC_CR2_RSTCAL) != 0)
+ ;
+ ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+ while ((ADC2->CR2 & ADC_CR2_CAL) != 0)
+ ;
+ ADC2->CR2 = 0;
+ RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
+
+ chopstx_claim_irq (&adc_intr, INTR_REQ_DMA1_Channel1);
+ return 0;
+}
+
+#include "board.h"
+#include "sys.h"
+
+static void
+get_adc_config (uint32_t config[4])
+{
+ config[2] = ADC_SQR1_NUM_CH(2);
+ switch (SYS_BOARD_ID)
+ {
+ case BOARD_ID_FST_01:
+ config[0] = 0;
+ config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
+ | ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5);
+ config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
+ | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9);
+ break;
+
+ case BOARD_ID_OLIMEX_STM32_H103:
+ case BOARD_ID_STBEE:
+ config[0] = ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5)
+ | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5);
+ config[1] = 0;
+ config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)
+ | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11);
+ break;
+
+ case BOARD_ID_STBEE_MINI:
+ config[0] = 0;
+ config[1] = ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5)
+ | ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5);
+ config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1)
+ | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2);
+ break;
+
+ case BOARD_ID_CQ_STARM:
+ case BOARD_ID_FST_01_00:
+ case BOARD_ID_MAPLE_MINI:
+ case BOARD_ID_STM32_PRIMER2:
+ case BOARD_ID_STM8S_DISCOVERY:
+ case BOARD_ID_ST_DONGLE:
+ case BOARD_ID_ST_NUCLEO_F103:
+ case BOARD_ID_NITROKEY_START:
+ default:
+ config[0] = 0;
+ config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
+ | ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5);
+ config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
+ | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN1);
+ break;
+ }
+}
+
+
+void
+adc_start (void)
+{
+ uint32_t config[4];
+
+ get_adc_config (config);
+
+ /* Use DMA channel 1. */
+ RCC->AHBENR |= RCC_AHBENR_DMA1EN;
+ DMA1_Channel1->CCR = STM32_DMA_CCR_RESET_VALUE;
+ DMA1->IFCR = 0xffffffff;
+
+ RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
+
+ ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+ | ADC_CR1_SCAN);
+ ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+ | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+ ADC1->SMPR1 = NEUG_ADC_SETTING1_SMPR1;
+ ADC1->SMPR2 = NEUG_ADC_SETTING1_SMPR2;
+ ADC1->SQR1 = ADC_SQR1_NUM_CH(NEUG_ADC_SETTING1_NUM_CHANNELS);
+ ADC1->SQR2 = 0;
+ ADC1->SQR3 = NEUG_ADC_SETTING1_SQR3;
+
+ ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+ | ADC_CR1_SCAN);
+ ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+ ADC2->SMPR1 = config[0];
+ ADC2->SMPR2 = config[1];
+ ADC2->SQR1 = config[2];
+ ADC2->SQR2 = 0;
+ ADC2->SQR3 = config[3];
+
+#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
+ /*
+ * We could just let ADC run continuously always and only enable DMA
+ * to receive stable data from ADC. But our purpose is not to get
+ * correct data but noise. In fact, we can get more noise when we
+ * start/stop ADC each time.
+ */
+ ADC2->CR2 = 0;
+ ADC1->CR2 = 0;
+#else
+ /* Start conversion. */
+ ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+ ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+ | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+#endif
+}
+
+uint32_t adc_buf[64];
+
+void
+adc_start_conversion (int offset, int count)
+{
+ DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR; /* SetPeripheral */
+ DMA1_Channel1->CMAR = (uint32_t)&adc_buf[offset]; /* SetMemory0 */
+ DMA1_Channel1->CNDTR = count; /* Counter */
+ DMA1_Channel1->CCR = NEUG_DMA_MODE | DMA_CCR1_EN; /* Mode */
+
+#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
+ /* Power on */
+ ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+ ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+ | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+ /*
+ * Start conversion. tSTAB is 1uS, but we don't follow the spec, to
+ * get more noise.
+ */
+ ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+ ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+ | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+#endif
+}
+
+
+static void adc_stop_conversion (void)
+{
+ DMA1_Channel1->CCR &= ~DMA_CCR1_EN;
+
+#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
+ ADC2->CR2 = 0;
+ ADC1->CR2 = 0;
+#endif
+}
+
+void
+adc_stop (void)
+{
+ ADC1->CR1 = 0;
+ ADC1->CR2 = 0;
+
+ ADC2->CR1 = 0;
+ ADC2->CR2 = 0;
+
+ RCC->AHBENR &= ~RCC_AHBENR_DMA1EN;
+ RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
+}
+
+
+static uint32_t adc_err;
+
+/*
+ * Return 0 on success.
+ * Return 1 on error.
+ */
+int
+adc_wait_completion (void)
+{
+ uint32_t flags;
+
+ while (1)
+ {
+ chopstx_poll (NULL, 1, &adc_intr);
+ flags = DMA1->ISR & STM32_DMA_ISR_MASK; /* Channel 1 interrupt cause. */
+ /*
+ * Clear interrupt cause of channel 1.
+ *
+ * Note that CGIFx=0, as CGIFx=1 clears all of GIF, HTIF, TCIF
+ * and TEIF.
+ */
+ DMA1->IFCR = (flags & ~1);
+
+ if ((flags & STM32_DMA_ISR_TEIF) != 0) /* DMA errors */
+ {
+ /* Should never happened. If any, it's coding error. */
+ /* Access an unmapped address space or alignment violation. */
+ adc_err++;
+ adc_stop_conversion ();
+ return 1;
+ }
+ else if ((flags & STM32_DMA_ISR_TCIF) != 0) /* Transfer complete */
+ {
+ adc_stop_conversion ();
+ return 0;
+ }
+ }
+}
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-04 18:36:28 +0000