diff options
| author | NIIBE Yutaka <gniibe@fsij.org> | 2013-11-02 14:23:44 +0900 |
|---|---|---|
| committer | NIIBE Yutaka <gniibe@fsij.org> | 2013-11-02 14:23:44 +0900 |
| commit | 9fe6cefdc0564b6bb3d938c0c1074d57a4b9500f (patch) | |
| tree | 915cfcf02076427abd45c4ca862d2062d947e50c /board | |
| parent | 5f14824977c1b7f281aa0b31cc8dbf93a649b504 (diff) | |
fix spurious interrupts, Gnuk pin-cir support
Diffstat (limited to 'board')
| -rw-r--r-- | board/board-fst-01-00.h | 18 | ||||
| -rw-r--r-- | board/board-fst-01.h | 31 | ||||
| -rw-r--r-- | board/board-olimex-stm32-h103.h | 18 | ||||
| -rw-r--r-- | board/board-stm8s-discovery.h | 45 |
4 files changed, 77 insertions, 35 deletions
diff --git a/board/board-fst-01-00.h b/board/board-fst-01-00.h index cedb2a5..a2bf9f9 100644 --- a/board/board-fst-01-00.h +++ b/board/board-fst-01-00.h @@ -1,11 +1,11 @@ #define FLASH_PAGE_SIZE 1024 -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HSECLK 8000000 +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HSECLK 8000000 -#define GPIO_USB_SET_TO_ENABLE 10 -#define GPIO_LED_SET_TO_EMIT 8 +#define GPIO_USB_SET_TO_ENABLE 10 +#define GPIO_LED_SET_TO_EMIT 8 /* * Port A setup. @@ -22,10 +22,10 @@ #define VAL_GPIO_CRL 0x88888888 /* PA7...PA0 */ #define VAL_GPIO_CRH 0x88811383 /* PA15...PA8 */ -#define GPIO_USB_BASE GPIOA_BASE -#define GPIO_LED_BASE GPIOA_BASE +#define GPIO_USB_BASE GPIOA_BASE +#define GPIO_LED_BASE GPIOA_BASE -#define RCC_APB2ENR_IOP_EN RCC_APB2ENR_IOPAEN -#define RCC_APB2RSTR_IOP_RST RCC_APB2RSTR_IOPARST +#define RCC_APB2ENR_IOP_EN RCC_APB2ENR_IOPAEN +#define RCC_APB2RSTR_IOP_RST RCC_APB2RSTR_IOPARST /* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */ diff --git a/board/board-fst-01.h b/board/board-fst-01.h index f9ab078..257ba72 100644 --- a/board/board-fst-01.h +++ b/board/board-fst-01.h @@ -1,11 +1,24 @@ #define FLASH_PAGE_SIZE 1024 -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 6 -#define STM32_HSECLK 12000000 +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 6 +#define STM32_HSECLK 12000000 -#define GPIO_USB_SET_TO_ENABLE 10 -#define GPIO_LED_SET_TO_EMIT 0 +#define GPIO_USB_SET_TO_ENABLE 10 +#define GPIO_LED_SET_TO_EMIT 0 + +/* For pin-cir settings of Gnuk */ +#define TIMx TIM2 +#define INTR_REQ_TIM TIM2_IRQ +#define AFIO_EXTICR_INDEX 0 +#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA +#define EXTI_PR EXTI_PR_PR2 +#define EXTI_IMR EXTI_IMR_MR2 +#define EXTI_FTSR_TR EXTI_FTSR_TR2 +#define INTR_REQ_EXTI EXTI2_IRQ +#define ENABLE_RCC_APB1 +#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM2EN +#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM2RST /* * Port A setup. @@ -42,11 +55,11 @@ #define VAL_GPIO_LED_CRL 0x88888883 /* PA7...PA0 */ #define VAL_GPIO_LED_CRH 0x88888888 /* PA15...PA8 */ -#define GPIO_USB_BASE GPIOA_BASE -#define GPIO_LED_BASE GPIOB_BASE +#define GPIO_USB_BASE GPIOA_BASE +#define GPIO_LED_BASE GPIOB_BASE -#define RCC_APB2ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN) -#define RCC_APB2RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST) +#define RCC_APB2ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN) +#define RCC_APB2RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST) /* NeuG settings for ADC2. */ #define NEUG_ADC_SETTING2_SMPR1 0 diff --git a/board/board-olimex-stm32-h103.h b/board/board-olimex-stm32-h103.h index d7470bc..a8cb7a0 100644 --- a/board/board-olimex-stm32-h103.h +++ b/board/board-olimex-stm32-h103.h @@ -1,11 +1,11 @@ #define FLASH_PAGE_SIZE 1024 -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HSECLK 8000000 +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HSECLK 8000000 -#define GPIO_USB_CLEAR_TO_ENABLE 11 -#define GPIO_LED_CLEAR_TO_EMIT 12 +#define GPIO_USB_CLEAR_TO_ENABLE 11 +#define GPIO_LED_CLEAR_TO_EMIT 12 /* * Port C setup. @@ -22,11 +22,11 @@ #define VAL_GPIO_CRL 0x44888888 /* PC7...PC0 */ #define VAL_GPIO_CRH 0x88837888 /* PC15...PC8 */ -#define GPIO_USB_BASE GPIOC_BASE -#define GPIO_LED_BASE GPIOC_BASE +#define GPIO_USB_BASE GPIOC_BASE +#define GPIO_LED_BASE GPIOC_BASE -#define RCC_APB2ENR_IOP_EN RCC_APB2ENR_IOPCEN -#define RCC_APB2RSTR_IOP_RST RCC_APB2RSTR_IOPCRST +#define RCC_APB2ENR_IOP_EN RCC_APB2ENR_IOPCEN +#define RCC_APB2RSTR_IOP_RST RCC_APB2RSTR_IOPCRST /* NeuG settings for ADC2. */ #define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \ diff --git a/board/board-stm8s-discovery.h b/board/board-stm8s-discovery.h index d20b1ab..25b3e84 100644 --- a/board/board-stm8s-discovery.h +++ b/board/board-stm8s-discovery.h @@ -1,11 +1,26 @@ #define FLASH_PAGE_SIZE 1024 -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HSECLK 8000000 +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HSECLK 8000000 #undef GPIO_USB_CLEAR_TO_ENABLE -#define GPIO_LED_SET_TO_EMIT 8 +#define GPIO_LED_SET_TO_EMIT 8 + +/* For pin-cir settings of Gnuk */ +#define TIMx TIM3 +#define INTR_REQ_TIM TIM3_IRQ +#define AFIO_EXTICR_INDEX 1 +#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR2_EXTI5_PB +#define EXTI_PR EXTI_PR_PR5 +#define EXTI_IMR EXTI_IMR_MR5 +#define EXTI_FTSR_TR EXTI_FTSR_TR5 +#define INTR_REQ_EXTI EXTI9_5_IRQ +#define ENABLE_RCC_APB1 +#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM3EN +#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM3RST +#define AFIO_MAPR_SOMETHING AFIO_MAPR_TIM3_REMAP_PARTIALREMAP + /* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */ /* * Port A setup. @@ -21,10 +36,24 @@ #define VAL_GPIO_CRL 0x88888888 /* PA7...PA0 */ #define VAL_GPIO_CRH 0x88811881 /* PA15...PA8 */ -#define GPIO_USB_BASE GPIOA_BASE -#define GPIO_LED_BASE GPIOA_BASE +#define GPIO_USB_BASE GPIOA_BASE +#define GPIO_LED_BASE GPIOA_BASE -#define RCC_APB2ENR_IOP_EN (RCC_APB2ENR_IOPAEN) -#define RCC_APB2RSTR_IOP_RST (RCC_APB2RSTR_IOPARST) +#define RCC_APB2ENR_IOP_EN \ + (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN) +#define RCC_APB2RSTR_IOP_RST \ + (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST) /* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */ + +#define GPIO_OTHER_BASE GPIOB_BASE +/* + * Port B setup. + * PB4 - (TIM3_CH1) input with pull-up + * PB5 - (TIM3_CH2) input with pull-up, connected to CIR module + * Everything input with pull-up except: + * PB0 - (TIM3_CH3) input with pull-down + */ +#define VAL_GPIO_OTHER_ODR 0xFFFFFFFE +#define VAL_GPIO_OTHER_CRL 0x88888888 /* PB7...PB0 */ +#define VAL_GPIO_OTHER_CRH 0x88888888 /* PB15...PB8 */ |