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authorNIIBE Yutaka <gniibe@fsij.org>2015-06-29 15:58:21 +0900
committerNIIBE Yutaka <gniibe@fsij.org>2015-06-29 15:58:21 +0900
commit97b4471cee86b4d7efc23d272db80fb89c7c8ab2 (patch)
treed066750a7976c25ae9e9c3f20ba8c7a91d5e7c6d /board/board-stbee.h
parent15ae2d8b3242c74c736f7d723125d0b6de367805 (diff)
Make it clear LED is mandatory.
Diffstat (limited to 'board/board-stbee.h')
-rw-r--r--board/board-stbee.h15
1 files changed, 7 insertions, 8 deletions
diff --git a/board/board-stbee.h b/board/board-stbee.h
index a12ec44..8104b5c 100644
--- a/board/board-stbee.h
+++ b/board/board-stbee.h
@@ -4,8 +4,11 @@
#define STM32_PLLMUL_VALUE 6
#define STM32_HSECLK 12000000
-#define GPIO_USB_CLEAR_TO_ENABLE 3
+#define GPIO_LED_BASE GPIOD_BASE
#define GPIO_LED_CLEAR_TO_EMIT 4
+#define GPIO_USB_BASE GPIOD_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE 3
+#define GPIO_OTHER_BASE GPIOA_BASE
/*
* Port A setup.
@@ -25,13 +28,9 @@
* PD3 - Push pull output (USB_DISC 1:USB-DISABLE 0:USB-ENABLE) 2MHz
* PD4 - Open Drain output 2MHz (LED1).
*/
-#define VAL_GPIO_ODR 0xFFFFFFFF
-#define VAL_GPIO_CRL 0x88862888 /* PD7...PD0 */
-#define VAL_GPIO_CRH 0x88888888 /* PD15...PD8 */
-
-#define GPIO_USB_BASE GPIOD_BASE
-#define GPIO_LED_BASE GPIOD_BASE
-#define GPIO_OTHER_BASE GPIOA_BASE
+#define VAL_GPIO_LED_ODR 0xFFFFFFFF
+#define VAL_GPIO_LED_CRL 0x88862888 /* PD7...PD0 */
+#define VAL_GPIO_LED_CRH 0x88888888 /* PD15...PD8 */
/* NeuG settings for ADC2. */
#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \