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authorNIIBE Yutaka <gniibe@fsij.org>2013-06-06 10:56:17 +0900
committerNIIBE Yutaka <gniibe@fsij.org>2013-06-06 10:56:17 +0900
commit60e0fbd189ec02c7817e7db649cb41f70d445525 (patch)
treec664a03502738f787d8229c2181be6f89b92338b /board/board-fst-01-00.h
parent5540f9b08a2b997aaa4bfbe3aa8bbaa571945eaa (diff)
update board-*.h
Diffstat (limited to 'board/board-fst-01-00.h')
-rw-r--r--board/board-fst-01-00.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/board/board-fst-01-00.h b/board/board-fst-01-00.h
new file mode 100644
index 0000000..2e9e768
--- /dev/null
+++ b/board/board-fst-01-00.h
@@ -0,0 +1,29 @@
+#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE 9
+#define STM32_HSECLK 8000000
+
+#define GPIO_USB_SET_TO_ENABLE 10
+#define GPIO_LED_SET_TO_EMIT 8
+
+/*
+ * Port A setup.
+ * PA0 - input with pull-up. AN0
+ * PA1 - input with pull-up. AN1
+ * PA8 - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * PA10 - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx - input with pull-up
+ */
+#define VAL_GPIO_ODR 0xFFFFE7FF
+#define VAL_GPIO_CRL 0x88888888 /* PA7...PA0 */
+#define VAL_GPIO_CRH 0x88811383 /* PA15...PA8 */
+
+#define GPIO_USB_BASE GPIOA_BASE
+#define GPIO_LED_BASE GPIOA_BASE
+
+#define RCC_APB2ENR_IOP_EN RCC_APB2ENR_IOPAEN
+#define RCC_APB2RSTR_IOP_RST RCC_APB2RSTR_IOPARST
+
+/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */