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| author | Anup Patel <anup.patel@wdc.com> | 2021-10-26 16:25:21 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-11-02 16:02:08 +0530 |
| commit | 013ba4ef3d94de67d040376535131012134ed54f (patch) | |
| tree | 215cb1ff0032b25bb1033f655146894f7492dd3e /lib/utils | |
| parent | c891acca172dfc60719419e19338508a83d97931 (diff) | |
lib: sbi: Fix GPA passed to __sbi_hfence_gvma_xyz() functions
The parameter passed to HFENCE.GVMA instruction in rs1 register
is guest physical address right shifted by 2 (i.e. divided by 4).
Unfortunately, we overlooked the semantics of rs1 registers for
HFENCE.GVMA instruction and never right shifted guest physical
address by 2. This issue did not manifest for hypervisors till
now because all H-extension implementations (such as QEMU, Spike,
Rocket Core FPGA, etc) we tried till now were conservatively
flushing everything upon any HFENCE.GVMA instruction.
This patch fixes GPA passed to __sbi_hfence_gvma_vmid_gpa()
and __sbi_hfence_gvma_gpa() functions.
Fixes: 331ff6a162c1 ("lib: Support stage1 and stage2 tlb flushing")
Reported-by: Ian Huang <ihuang@ventanamicro.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Diffstat (limited to 'lib/utils')
0 files changed, 0 insertions, 0 deletions