diff options
| author | Atish Patra <atish.patra@wdc.com> | 2021-07-10 09:18:13 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-07-11 10:38:02 +0530 |
| commit | 37f9b0f2f265b2f312d974fb8d100b85b3faf94f (patch) | |
| tree | 914b0a37f87f7fe6a8bee2f248019bfa15012055 /lib/sbi/sbi_pmu.c | |
| parent | ae72ec091508196e29c07ae46bca106373d31e39 (diff) | |
lib: sbi: Implement SBI PMU extension
RISC-V SBI specfication 0.3 defines a PMU extension that allows supervisor
mode to start/stop/configure pmu related events. This patch implements
all of the functionality defined in the specification.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_pmu.c')
| -rw-r--r-- | lib/sbi/sbi_pmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index d01e248..4092e6f 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -375,7 +375,7 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx, if (!mhpmevent_val || ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX) return SBI_EFAIL; - /* TODO: The upper 8 bits of mhpmevent is reserved by sscofpmf extension. + /* TODO: The upper 16 bits of mhpmevent is reserved by sscofpmf extension. * Update those bits based on the flags received from supervisor. * The OVF bit also should be cleared here in case it was not cleared * during event stop. |