diff options
| author | Anup Patel <anup.patel@wdc.com> | 2020-03-19 21:30:02 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-03-28 13:32:14 +0530 |
| commit | fe37d7da29f67ae8ccc31f06e0f3e6c9a6b58054 (patch) | |
| tree | edf5816ec411be7b554ce2bb9af5f17dc633b9a0 /lib/sbi/sbi_misaligned_ldst.c | |
| parent | 5a7bd0c88d7455de46143ccd9c74a40162bd3611 (diff) | |
lib: sbi_misaligned_ldst: Remove mcause, scratch and hartid parameters
We remove mcause, scratch and hartid parameters from various functions
for misaligned load/store handling because we can always get current
HART id and current scratch pointer using just one CSR access.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_misaligned_ldst.c')
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 7c15a40..29d79bb 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -21,10 +21,8 @@ union reg_data { u64 data_u64; }; -int sbi_misaligned_load_handler(u32 hartid, ulong mcause, - ulong addr, ulong tval2, ulong tinst, - struct sbi_trap_regs *regs, - struct sbi_scratch *scratch) +int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst, + struct sbi_trap_regs *regs) { ulong insn; union reg_data val; @@ -110,7 +108,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, #endif } else { uptrap.epc = regs->mepc; - uptrap.cause = mcause; + uptrap.cause = CAUSE_MISALIGNED_LOAD; uptrap.tval = addr; uptrap.tval2 = tval2; uptrap.tinst = tinst; @@ -141,10 +139,8 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, return 0; } -int sbi_misaligned_store_handler(u32 hartid, ulong mcause, - ulong addr, ulong tval2, ulong tinst, - struct sbi_trap_regs *regs, - struct sbi_scratch *scratch) +int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst, + struct sbi_trap_regs *regs) { ulong insn; union reg_data val; @@ -221,7 +217,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, #endif } else { uptrap.epc = regs->mepc; - uptrap.cause = mcause; + uptrap.cause = CAUSE_MISALIGNED_STORE; uptrap.tval = addr; uptrap.tval2 = tval2; uptrap.tinst = tinst; |