diff options
| author | Anup Patel <anup.patel@wdc.com> | 2019-08-17 20:54:40 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-09-30 15:35:43 +0530 |
| commit | 7d4420bd6929ef3f2c761c262dbc3f7f2ae150c2 (patch) | |
| tree | dd82311f1464491c0a7f7df116961ca64aab5a33 /lib/sbi/sbi_misaligned_ldst.c | |
| parent | a14e7ee82c2723f18cf2d1c7f1a88d88766a6018 (diff) | |
include: Extend get_insn() to read instruction from VS/VU mode
Current implementation of get_insn() is not suitable for reading
instruction from VS/VU mode because we have to set SSTATUS_MXR bit
in VSSTATUS CSR for reading instruction from VS/VU mode.
This patch extends get_insn() to read instruction from VS/VU mode.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_misaligned_ldst.c')
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index e0f10bc..10c467c 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -27,9 +27,14 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, { union reg_data val; struct unpriv_trap uptrap; - ulong insn = get_insn(regs->mepc, scratch, &uptrap); ulong addr = csr_read(CSR_MTVAL); int i, fp = 0, shift = 0, len = 0; +#if __riscv_xlen == 32 + bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE; +#else + bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE; +#endif + ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap); if (uptrap.cause) return sbi_trap_redirect(regs, scratch, regs->mepc, @@ -129,9 +134,14 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, { union reg_data val; struct unpriv_trap uptrap; - ulong insn = get_insn(regs->mepc, scratch, &uptrap); ulong addr = csr_read(CSR_MTVAL); int i, len = 0; +#if __riscv_xlen == 32 + bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE; +#else + bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE; +#endif + ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap); if (uptrap.cause) return sbi_trap_redirect(regs, scratch, regs->mepc, |