diff options
| author | Anup Patel <anup.patel@wdc.com> | 2019-12-12 22:23:30 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-12-16 14:48:26 +0530 |
| commit | 2be424bd28560d5399788ed16f663f7785a8c5f9 (patch) | |
| tree | 6c70bfa0031276961cc79c4c2c40ed75889302d6 /lib/sbi/sbi_misaligned_ldst.c | |
| parent | 086dbdfc926301c8273a64a064452b7d97f0d9a4 (diff) | |
lib: Extend trap redirection for hypervisor v0.5 spec
The hypervisor v0.5 spec introduces two new CSRs for both M-mode
and HS-mode which need to be considered when redirecting traps
hence this patch.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_misaligned_ldst.c')
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 57c7af4..314b2f3 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -22,12 +22,12 @@ union reg_data { }; int sbi_misaligned_load_handler(u32 hartid, ulong mcause, + ulong addr, ulong tval2, ulong tinst, struct sbi_trap_regs *regs, struct sbi_scratch *scratch) { union reg_data val; struct sbi_trap_info uptrap; - ulong addr = csr_read(CSR_MTVAL); int i, fp = 0, shift = 0, len = 0; ulong insn = sbi_get_insn(regs->mepc, scratch, &uptrap); @@ -101,6 +101,8 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, uptrap.epc = regs->mepc; uptrap.cause = mcause; uptrap.tval = addr; + uptrap.tval2 = tval2; + uptrap.tinst = tinst; return sbi_trap_redirect(regs, &uptrap, scratch); } @@ -129,12 +131,12 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, } int sbi_misaligned_store_handler(u32 hartid, ulong mcause, + ulong addr, ulong tval2, ulong tinst, struct sbi_trap_regs *regs, struct sbi_scratch *scratch) { union reg_data val; struct sbi_trap_info uptrap; - ulong addr = csr_read(CSR_MTVAL); int i, len = 0; ulong insn = sbi_get_insn(regs->mepc, scratch, &uptrap); @@ -199,6 +201,8 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, uptrap.epc = regs->mepc; uptrap.cause = mcause; uptrap.tval = addr; + uptrap.tval2 = tval2; + uptrap.tinst = tinst; return sbi_trap_redirect(regs, &uptrap, scratch); } |