diff options
| author | Anup Patel <Anup.Patel@wdc.com> | 2019-07-25 05:05:03 +0000 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-07-26 15:49:49 +0530 |
| commit | 0f18b3fe0adda745b3ac80f7b79ce2b8512e2e95 (patch) | |
| tree | d0150cb3b9a353f89985cec24b340c0058a9812a /lib/sbi/sbi_misaligned_ldst.c | |
| parent | 85546a5477d470ab84922b3bc28debe127a47f05 (diff) | |
lib: Allow compiling without FP support
Currently, we mandate 'F' and 'D' extension in riscv_fp.h so that
misaligned load/store emulation has access to FP registers.
The above is too restrictive and we should certainly allow compilation
for soft-FP toolchains and explicit PLATFORM_RISCV_ISA not having 'F'
and 'D' extensions.
This patch extends riscv_fp.h and misaligned load/store emulation to
allow compiling OpenSBI without FP support.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'lib/sbi/sbi_misaligned_ldst.c')
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 7f911c3..1c4e5df 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -41,12 +41,14 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, } else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) { len = 4; #endif +#ifdef __riscv_flen } else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) { fp = 1; len = 8; } else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) { fp = 1; len = 4; +#endif } else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) { len = 2; shift = 8 * (sizeof(ulong) - len); @@ -71,6 +73,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, ((insn >> SH_RD) & 0x1f)) { len = 4; shift = 8 * (sizeof(ulong) - len); +#ifdef __riscv_flen } else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) { fp = 1; len = 8; @@ -88,8 +91,10 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, len = 4; #endif #endif +#endif } else - return SBI_EILL; + return sbi_trap_redirect(regs, scratch, regs->mepc, + mcause, addr); val.data_u64 = 0; for (i = 0; i < len; i++) { @@ -104,10 +109,12 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, if (!fp) SET_RD(insn, regs, val.data_ulong << shift >> shift); +#ifdef __riscv_flen else if (len == 8) SET_F64_RD(insn, regs, val.data_u64); else SET_F32_RD(insn, regs, val.data_ulong); +#endif regs->mepc += INSN_LEN(insn); @@ -132,12 +139,14 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) { len = 8; #endif +#ifdef __riscv_flen } else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) { len = 8; val.data_u64 = GET_F64_RS2(insn, regs); } else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) { len = 4; val.data_ulong = GET_F32_RS2(insn, regs); +#endif } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) { len = 2; #ifdef __riscv_compressed @@ -157,6 +166,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, ((insn >> SH_RD) & 0x1f)) { len = 4; val.data_ulong = GET_RS2C(insn, regs); +#ifdef __riscv_flen } else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) { len = 8; val.data_u64 = GET_F64_RS2S(insn, regs); @@ -172,8 +182,10 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, val.data_ulong = GET_F32_RS2C(insn, regs); #endif #endif +#endif } else - return SBI_EILL; + return sbi_trap_redirect(regs, scratch, regs->mepc, + mcause, addr); for (i = 0; i < len; i++) { store_u8((void *)(addr + i), val.data_bytes[i], |