diff options
| author | Anup Patel <anup.patel@wdc.com> | 2019-12-12 22:23:30 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-12-16 14:48:26 +0530 |
| commit | 2be424bd28560d5399788ed16f663f7785a8c5f9 (patch) | |
| tree | 6c70bfa0031276961cc79c4c2c40ed75889302d6 /lib/sbi/sbi_illegal_insn.c | |
| parent | 086dbdfc926301c8273a64a064452b7d97f0d9a4 (diff) | |
lib: Extend trap redirection for hypervisor v0.5 spec
The hypervisor v0.5 spec introduces two new CSRs for both M-mode
and HS-mode which need to be considered when redirecting traps
hence this patch.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_illegal_insn.c')
| -rw-r--r-- | lib/sbi/sbi_illegal_insn.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/sbi/sbi_illegal_insn.c b/lib/sbi/sbi_illegal_insn.c index 021ae37..e3c7809 100644 --- a/lib/sbi/sbi_illegal_insn.c +++ b/lib/sbi/sbi_illegal_insn.c @@ -29,6 +29,8 @@ static int truly_illegal_insn(ulong insn, u32 hartid, ulong mcause, trap.epc = regs->mepc; trap.cause = mcause; trap.tval = insn; + trap.tval2 = 0; + trap.tinst = 0; return sbi_trap_redirect(regs, &trap, scratch); } @@ -131,11 +133,10 @@ static illegal_insn_func illegal_insn_table[32] = { truly_illegal_insn /* 31 */ }; -int sbi_illegal_insn_handler(u32 hartid, ulong mcause, +int sbi_illegal_insn_handler(u32 hartid, ulong mcause, ulong insn, struct sbi_trap_regs *regs, struct sbi_scratch *scratch) { - ulong insn = csr_read(CSR_MTVAL); struct sbi_trap_info uptrap; if (unlikely((insn & 3) != 3)) { |