diff options
| author | Anup Patel <anup.patel@wdc.com> | 2020-06-06 17:33:48 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-06-15 09:24:27 +0530 |
| commit | e2c3f01af4329aa7e9009edee13b7cfdf379071f (patch) | |
| tree | 9b4b0d6ecd076ef0f14c514433a251a8bb64487d /lib/sbi/sbi_hfence.S | |
| parent | 32f87e5a8668445097473d4ad3ab5a0de7b1dd6f (diff) | |
lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va()
The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and
__sbi_hfence_vvma_asid_va() functions are swapped so we fix it.
Currently, we did not face any issues because QEMU does a full
TLB flush for all HFENCE instructions.
We also improve documentation of HFENCE.GVMA and HFENCE.VVMA
instruction encoding.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_hfence.S')
| -rw-r--r-- | lib/sbi/sbi_hfence.S | 84 |
1 files changed, 72 insertions, 12 deletions
diff --git a/lib/sbi/sbi_hfence.S b/lib/sbi/sbi_hfence.S index 30a6e9f..d05becb 100644 --- a/lib/sbi/sbi_hfence.S +++ b/lib/sbi/sbi_hfence.S @@ -9,67 +9,127 @@ */ /* - * Instruction encoding of hfence.gvma is: + * HFENCE.GVMA rs1, rs2 + * HFENCE.GVMA zero, rs2 + * HFENCE.GVMA rs1 + * HFENCE.GVMA + * + * rs1!=zero and rs2!=zero ==> HFENCE.GVMA rs1, rs2 + * rs1==zero and rs2!=zero ==> HFENCE.GVMA zero, rs2 + * rs1!=zero and rs2==zero ==> HFENCE.GVMA rs1 + * rs1==zero and rs2==zero ==> HFENCE.GVMA + * + * Instruction encoding of HFENCE.GVMA is: * 0110001 rs2(5) rs1(5) 000 00000 1110011 */ .align 3 .global __sbi_hfence_gvma_vmid_gpa __sbi_hfence_gvma_vmid_gpa: - /* hfence.gvma a1, a0 */ - .word 0x62a60073 + /* + * rs1 = a0 (GPA) + * rs2 = a1 (VMID) + * HFENCE.GVMA a0, a1 + * 0110001 01011 01010 000 00000 1110011 + */ + .word 0x62b50073 ret .align 3 .global __sbi_hfence_gvma_vmid __sbi_hfence_gvma_vmid: - /* hfence.gvma zero, a0 */ + /* + * rs1 = zero + * rs2 = a0 (VMID) + * HFENCE.GVMA zero, a0 + * 0110001 01010 00000 000 00000 1110011 + */ .word 0x62a00073 ret .align 3 .global __sbi_hfence_gvma_gpa __sbi_hfence_gvma_gpa: - /* hfence.gvma a0 */ + /* + * rs1 = a0 (GPA) + * rs2 = zero + * HFENCE.GVMA a0 + * 0110001 00000 01010 000 00000 1110011 + */ .word 0x62050073 ret .align 3 .global __sbi_hfence_gvma_all __sbi_hfence_gvma_all: - /* hfence.gvma */ + /* + * rs1 = zero + * rs2 = zero + * HFENCE.GVMA + * 0110001 00000 00000 000 00000 1110011 + */ .word 0x62000073 ret /* - * Instruction encoding of hfence.bvma is: + * HFENCE.VVMA rs1, rs2 + * HFENCE.VVMA zero, rs2 + * HFENCE.VVMA rs1 + * HFENCE.VVMA + * + * rs1!=zero and rs2!=zero ==> HFENCE.VVMA rs1, rs2 + * rs1==zero and rs2!=zero ==> HFENCE.VVMA zero, rs2 + * rs1!=zero and rs2==zero ==> HFENCE.VVMA rs1 + * rs1==zero and rs2==zero ==> HFENCE.vVMA + * + * Instruction encoding of HFENCE.VVMA is: * 0010001 rs2(5) rs1(5) 000 00000 1110011 */ .align 3 .global __sbi_hfence_vvma_asid_va __sbi_hfence_vvma_asid_va: - /* hfence.bvma a1, a0 */ - .word 0x22a60073 + /* + * rs1 = a0 (VA) + * rs2 = a1 (ASID) + * HFENCE.VVMA a0, a1 + * 0010001 01011 01010 000 00000 1110011 + */ + .word 0x22b50073 ret .align 3 .global __sbi_hfence_vvma_asid __sbi_hfence_vvma_asid: - /* hfence.bvma zero, a0 */ + /* + * rs1 = zero + * rs2 = a0 (ASID) + * HFENCE.VVMA zero, a0 + * 0010001 01010 00000 000 00000 1110011 + */ .word 0x22a00073 ret .align 3 .global __sbi_hfence_vvma_va __sbi_hfence_vvma_va: - /* hfence.bvma a0 */ + /* + * rs1 = a0 (VA) + * rs2 = zero + * HFENCE.VVMA zero, a0 + * 0010001 00000 01010 000 00000 1110011 + */ .word 0x22050073 ret .align 3 .global __sbi_hfence_vvma_all __sbi_hfence_vvma_all: - /* hfence.bvma */ + /* + * rs1 = zero + * rs2 = zero + * HFENCE.VVMA + * 0010001 00000 00000 000 00000 1110011 + */ .word 0x22000073 ret |