diff options
| author | Atish Patra <atish.patra@wdc.com> | 2021-07-10 09:18:03 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-07-11 10:11:10 +0530 |
| commit | fde28fadc2603c7c7a4afa7c2e7b96cc7b11d2e2 (patch) | |
| tree | 5b473fe4342a31d47ba988d93c8730409e28a993 /include | |
| parent | 3e8b31aca988955800d15329f1d4e48b4fbe7233 (diff) | |
lib: sbi: Detect mcountinihibit support at runtime
RISC-V ISA specification v1.11 defined mcountinhibit CSR that allows
software to stop any counter from incrementing. The SBI PMU extension
depends on this CSR support in hardware.
Define mcountinhibit as a hart specific feature and detect it at runtime.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/sbi_hart.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 031c7b0..9e317c5 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -18,8 +18,10 @@ enum sbi_hart_features { SBI_HART_HAS_SCOUNTEREN = (1 << 0), /** Hart has M-mode counter enable */ SBI_HART_HAS_MCOUNTEREN = (1 << 1), + /** Hart has counter inhibit CSR */ + SBI_HART_HAS_MCOUNTINHIBIT = (1 << 2), /** HART has timer csr implementation in hardware */ - SBI_HART_HAS_TIME = (1 << 2), + SBI_HART_HAS_TIME = (1 << 3), /** Last index of Hart features*/ SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME, |