diff options
| author | Atish Patra <atish.patra@wdc.com> | 2019-11-24 23:33:49 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-12-23 09:12:19 +0530 |
| commit | 331ff6a162c1eeb61919db42162584c5f27d0fce (patch) | |
| tree | e2d88706f4a163ae110d38f3d6295c963b424dc2 /include/sbi/sbi_tlb.h | |
| parent | 94072025325b639d603f428366b53b470e625f64 (diff) | |
lib: Support stage1 and stage2 tlb flushing
The hypervisor specification support hfence calls which can be used
issue tlb flush requests at both level of address translation. Currently,
these requests are issued only via SBI which are defined in v0.2.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'include/sbi/sbi_tlb.h')
| -rw-r--r-- | include/sbi/sbi_tlb.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/sbi/sbi_tlb.h b/include/sbi/sbi_tlb.h index d1d6f22..83f9458 100644 --- a/include/sbi/sbi_tlb.h +++ b/include/sbi/sbi_tlb.h @@ -24,7 +24,10 @@ enum sbi_tlb_info_types { SBI_TLB_FLUSH_VMA, SBI_TLB_FLUSH_VMA_ASID, - SBI_TLB_FLUSH_VMA_VMID, + SBI_TLB_FLUSH_GVMA, + SBI_TLB_FLUSH_GVMA_VMID, + SBI_TLB_FLUSH_VVMA, + SBI_TLB_FLUSH_VVMA_ASID, SBI_ITLB_FLUSH }; |