diff options
| author | Olof Johansson <olof@lixom.net> | 2019-04-10 17:41:52 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-04-24 09:49:46 +0530 |
| commit | 10baa64c02f6746fd506136e0693aa2d592574fb (patch) | |
| tree | da00e48f0cb5d1434cbc7c31bb6ca15efa7d4564 /include/sbi/riscv_fp.h | |
| parent | fbf986ac2a0b926ae97e6796b87e366610d7589e (diff) | |
all: run clang-format and update checked-in files
Noisy commit, no functional changes.
Generated with an current upstream clang-format and:
clang-format -i $(find . -name \*.[ch])
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include/sbi/riscv_fp.h')
| -rw-r--r-- | include/sbi/riscv_fp.h | 71 |
1 files changed, 47 insertions, 24 deletions
diff --git a/include/sbi/riscv_fp.h b/include/sbi/riscv_fp.h index 9e2e082..a8d4c51 100644 --- a/include/sbi/riscv_fp.h +++ b/include/sbi/riscv_fp.h @@ -21,28 +21,49 @@ #ifdef __riscv_flen -#define GET_F32_REG(insn, pos, regs) ({ \ - register s32 value asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ - ulong tmp; \ - asm ("1: auipc %0, %%pcrel_hi(get_f32_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp), "+&r"(value) :: "t0"); \ - value; }) -#define SET_F32_REG(insn, pos, regs, val) ({ \ - register u32 value asm("a0") = (val); \ - ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ - ulong tmp; \ - asm volatile ("1: auipc %0, %%pcrel_hi(put_f32_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(value), "r"(offset) : "t0"); }) +#define GET_F32_REG(insn, pos, regs) \ + ({ \ + register s32 value asm("a0") = \ + SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ + ulong tmp; \ + asm("1: auipc %0, %%pcrel_hi(get_f32_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \ + : "=&r"(tmp), "+&r"(value)::"t0"); \ + value; \ + }) +#define SET_F32_REG(insn, pos, regs, val) \ + ({ \ + register u32 value asm("a0") = (val); \ + ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ + ulong tmp; \ + asm volatile( \ + "1: auipc %0, %%pcrel_hi(put_f32_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \ + : "=&r"(tmp) \ + : "r"(value), "r"(offset) \ + : "t0"); \ + }) #define init_fp_reg(i) SET_F32_REG((i) << 3, 3, 0, 0) -#define GET_F64_REG(insn, pos, regs) ({ \ - register ulong value asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ - ulong tmp; \ - asm ("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp), "+&r"(value) :: "t0"); \ - sizeof(ulong) == 4 ? *(int64_t*)value : (int64_t)value; }) -#define SET_F64_REG(insn, pos, regs, val) ({ \ - uint64_t __val = (val); \ - register ulong value asm("a0") = sizeof(ulong) == 4 ? (ulong)&__val : (ulong)__val; \ - ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ - ulong tmp; \ - asm volatile ("1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(value), "r"(offset) : "t0"); }) +#define GET_F64_REG(insn, pos, regs) \ + ({ \ + register ulong value asm("a0") = \ + SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ + ulong tmp; \ + asm("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \ + : "=&r"(tmp), "+&r"(value)::"t0"); \ + sizeof(ulong) == 4 ? *(int64_t *)value : (int64_t)value; \ + }) +#define SET_F64_REG(insn, pos, regs, val) \ + ({ \ + uint64_t __val = (val); \ + register ulong value asm("a0") = \ + sizeof(ulong) == 4 ? (ulong)&__val : (ulong)__val; \ + ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ + ulong tmp; \ + asm volatile( \ + "1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \ + : "=&r"(tmp) \ + : "r"(value), "r"(offset) \ + : "t0"); \ + }) #define GET_FCSR() csr_read(CSR_FCSR) #define SET_FCSR(value) csr_write(CSR_FCSR, (value)) #define GET_FRM() csr_read(CSR_FRM) @@ -50,7 +71,7 @@ #define GET_FFLAGS() csr_read(CSR_FFLAGS) #define SET_FFLAGS(value) csr_write(CSR_FFLAGS, (value)) -#define SET_FS_DIRTY() ((void) 0) +#define SET_FS_DIRTY() ((void)0) #else #error "Floating point emulation not supported.\n" @@ -62,8 +83,10 @@ #define GET_F64_RS1(insn, regs) (GET_F64_REG(insn, 15, regs)) #define GET_F64_RS2(insn, regs) (GET_F64_REG(insn, 20, regs)) #define GET_F64_RS3(insn, regs) (GET_F64_REG(insn, 27, regs)) -#define SET_F32_RD(insn, regs, val) (SET_F32_REG(insn, 7, regs, val), SET_FS_DIRTY()) -#define SET_F64_RD(insn, regs, val) (SET_F64_REG(insn, 7, regs, val), SET_FS_DIRTY()) +#define SET_F32_RD(insn, regs, val) \ + (SET_F32_REG(insn, 7, regs, val), SET_FS_DIRTY()) +#define SET_F64_RD(insn, regs, val) \ + (SET_F64_REG(insn, 7, regs, val), SET_FS_DIRTY()) #define GET_F32_RS2C(insn, regs) (GET_F32_REG(insn, 2, regs)) #define GET_F32_RS2S(insn, regs) (GET_F32_REG(RVC_RS2S(insn), 0, regs)) |