diff options
| author | Anup Patel <anup.patel@wdc.com> | 2018-12-31 11:19:20 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-01-02 09:57:12 +0530 |
| commit | e0d6914b3c40c1609ccf196fa448ea6880ff23d5 (patch) | |
| tree | cb6636a9da04ea258adb177dbc5060e647ca72ae /firmware | |
| parent | 24bfa687fc85f0c8b0b2ed60151e44e9b7c43d3b (diff) | |
include: Move RISCV_SCRATCH_xyz defines to sbi_scratch.h
The struct sbi_scratch related defines RISCV_SCRATCH_xyz should
be in sbi_scratch.h so that we can keep these defines in-sync
with changes in struct sbi_scratch.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/fw_base.S | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index d426f15..d872061 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -9,6 +9,7 @@ #include <sbi/riscv_asm.h> #include <sbi/riscv_encoding.h> +#include <sbi/sbi_scratch.h> .align 3 .section .entry, "ax", %progbits @@ -146,34 +147,34 @@ _start_warm: add tp, tp, a5 mul a5, s8, s6 sub tp, tp, a5 - li a5, RISCV_SCRATCH_SIZE + li a5, SBI_SCRATCH_SIZE sub tp, tp, a5 csrw mscratch, tp /* Initialize scratch space */ - REG_S zero, RISCV_SCRATCH_TMP0_OFFSET(tp) + REG_S zero, SBI_SCRATCH_TMP0_OFFSET(tp) la a4, _fw_start la a5, _fw_end mul t0, s7, s8 add a5, a5, t0 sub a5, a5, a4 - REG_S a4, RISCV_SCRATCH_FW_START_OFFSET(tp) - REG_S a5, RISCV_SCRATCH_FW_SIZE_OFFSET(tp) + REG_S a4, SBI_SCRATCH_FW_START_OFFSET(tp) + REG_S a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp) /* Note: fw_next_arg1() uses a0, a1, and ra */ call fw_next_arg1 - REG_S a0, RISCV_SCRATCH_NEXT_ARG1_OFFSET(tp) + REG_S a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) /* Note: fw_next_addr() uses a0, a1, and ra */ call fw_next_addr - REG_S a0, RISCV_SCRATCH_NEXT_ADDR_OFFSET(tp) + REG_S a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp) li a4, PRV_S - REG_S a4, RISCV_SCRATCH_NEXT_MODE_OFFSET(tp) + REG_S a4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp) la a4, _start_warm - REG_S a4, RISCV_SCRATCH_WARMBOOT_ADDR_OFFSET(tp) + REG_S a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp) la a4, platform - REG_S a4, RISCV_SCRATCH_PLATFORM_ADDR_OFFSET(tp) + REG_S a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp) la a4, _hartid_to_scratch - REG_S a4, RISCV_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) - REG_S zero, RISCV_SCRATCH_IPI_TYPE_OFFSET(tp) + REG_S a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) + REG_S zero, SBI_SCRATCH_IPI_TYPE_OFFSET(tp) /* Setup stack */ add sp, tp, zero @@ -211,7 +212,7 @@ _hartid_to_scratch: add s1, s1, s2 mul s2, s0, a0 sub s1, s1, s2 - li s2, RISCV_SCRATCH_SIZE + li s2, SBI_SCRATCH_SIZE sub a0, s1, s2 REG_L s0, (sp) REG_L s1, (__SIZEOF_POINTER__)(sp) |