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authorPanagiotis Peristerakis <perister@ics.forth.gr>2019-06-27 18:28:50 +0300
committerAnup Patel <anup@brainfault.org>2019-06-29 17:04:06 +0530
commit3048f979cab3d0f42461bd4d96a4bdecf1791f62 (patch)
treef534aacb23313280277aa1c3cc5cba0d4525e868 /docs/platform/ariane-fpga.md
parentb44e844880d05c14ea90604c8d2f4d07878a18b9 (diff)
Add documentation for Ariane FPGA platform
Signed-off-by: Panagiotis Peristerakis <perister@ics.forth.gr>
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+Ariane FPGA SoC Platform
+==========================
+Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set.
+The Ariane FPGA development platform is based on FPGA FPGA SoC(which currently supports only Genesys 2 board) and is capable
+of running Linux.
+ The FPGA SoC currently contains the following peripherals:
+- DDR3 memory controller
+- SPI controller to conncet to an SDCard
+- Ethernet controller
+- JTAG port (see debugging section below)
+- Bootrom containing zero stage bootloader and device tree.
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=ariane-fpga* parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *Ariane FPGA* platform does not have any platform-specific
+options.
+
+Building Ariane FPGA Platform
+-----------------------------
+**Linux Kernel Payload**
+
+
+```
+make PLATFORM=ariane-fpga FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+```
+
+Booting Ariane FPGA Platform
+-----------------------------
+
+**Linux Kernel Payload**
+
+As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will directly
+boot into Linux directly after powered on.