diff options
| author | Nylon Chen <nylon7@andestech.com> | 2020-06-09 13:56:57 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-06-10 09:27:46 +0530 |
| commit | 980290651fc28b063633a6a59b63a6938ee13cff (patch) | |
| tree | d834f363a0e349cea11aa7bb9c1bcaf7e8b96fbf | |
| parent | 106b888e201bea80eb6c31ce2ed851884a5e0ec7 (diff) | |
platform: Add AE350 platform specific SBI handler
We add AE350 platform specific SBI handler to implement
AE350 specific SBI calls.
Signed-off-by: Nylon Chen <nylon7@andestech.com>
Reviewed-by: Anup Patel <Anup.Patel@wdc.com>
Reviewed-by: Atish Patra <Atish.Patra@wdc.com>
| -rw-r--r-- | platform/andes/ae350/platform.c | 18 | ||||
| -rw-r--r-- | platform/andes/ae350/platform.h | 15 |
2 files changed, 30 insertions, 3 deletions
diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c index 9f013d8..c75affe 100644 --- a/platform/andes/ae350/platform.c +++ b/platform/andes/ae350/platform.c @@ -121,6 +121,20 @@ static int ae350_system_reset(u32 type) return 0; } +/* Vendor-Specific SBI handler */ +static int ae350_vendor_ext_provider(long extid, long funcid, + unsigned long *args, unsigned long *out_value, + struct sbi_trap_info *out_trap) +{ + int ret = 0; + switch (funcid) { + default: + sbi_printf("Unsupported vendor sbi call : %ld\n", funcid); + asm volatile("ebreak"); + } + return ret; +} + /* Platform descriptor. */ const struct sbi_platform_operations platform_ops = { .final_init = ae350_final_init, @@ -140,7 +154,9 @@ const struct sbi_platform_operations platform_ops = { .timer_event_start = plmt_timer_event_start, .timer_event_stop = plmt_timer_event_stop, - .system_reset = ae350_system_reset + .system_reset = ae350_system_reset, + + .vendor_ext_provider = ae350_vendor_ext_provider }; const struct sbi_platform platform = { diff --git a/platform/andes/ae350/platform.h b/platform/andes/ae350/platform.h index 062b656..03cd421 100644 --- a/platform/andes/ae350/platform.h +++ b/platform/andes/ae350/platform.h @@ -29,8 +29,19 @@ #define AE350_UART_REG_SHIFT 2 #define AE350_UART_REG_WIDTH 0 -/* nds mcache_ctl register*/ -#define CSR_MCACHECTL 0x7ca + +enum sbi_ext_andes_fid { + SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0, + SBI_EXT_ANDES_GET_MMISC_CTL_STATUS, + SBI_EXT_ANDES_SET_MCACHE_CTL, + SBI_EXT_ANDES_SET_MMISC_CTL, + SBI_EXT_ANDES_ICACHE_OP, + SBI_EXT_ANDES_DCACHE_OP, + SBI_EXT_ANDES_L1CACHE_I_PREFETCH, + SBI_EXT_ANDES_L1CACHE_D_PREFETCH, + SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE, + SBI_EXT_ANDES_WRITE_AROUND, +}; #define V5_MCACHE_CTL_IC_EN_OFFSET 0 #define V5_MCACHE_CTL_DC_EN_OFFSET 1 |