diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2019-01-23 09:29:55 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-02-08 09:18:46 +0530 |
| commit | 4f32b13802c118c381a562747467b829f7a14e78 (patch) | |
| tree | 07654457fdbd1b922bb9eb520b5d4fdba41b5fd5 | |
| parent | f9b033e57769bf24fc13293afdd43c1979527615 (diff) | |
firmware: Use lw instead of lwu for 32-bit architectures
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | firmware/fw_base.S | 14 | ||||
| -rw-r--r-- | include/sbi/sbi_unpriv.h | 8 |
2 files changed, 22 insertions, 0 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index 63cb64c..fb27ea3 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -69,7 +69,11 @@ _prev_arg1_override_done: add t0, a1, zero and t0, t0, a3 /* t2 = source FDT size in big-endian */ +#if __riscv_xlen == 64 lwu t2, 4(t0) +#else + lw t2, 4(t0) +#endif /* t3 = bit[15:8] of FDT size */ add t3, t2, zero srli t3, t3, 16 @@ -132,8 +136,13 @@ _start_warm: */ csrr s6, mhartid la a4, platform +#if __riscv_xlen == 64 lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4) +#else + lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) + lw s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4) +#endif /* HART ID should be within expected limit */ csrr s6, mhartid @@ -202,8 +211,13 @@ _hartid_to_scratch: * s2 -> Temporary */ la s2, platform +#if __riscv_xlen == 64 lwu s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) lwu s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2) +#else + lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) + lw s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2) +#endif mul s2, s2, s0 la s1, _fw_end add s1, s1, s2 diff --git a/include/sbi/sbi_unpriv.h b/include/sbi/sbi_unpriv.h index 2da5785..11ece0d 100644 --- a/include/sbi/sbi_unpriv.h +++ b/include/sbi/sbi_unpriv.h @@ -77,7 +77,11 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus) ulong val; #ifndef __riscv_compressed asm ("csrrs %[mstatus], mstatus, %[mprv]\n" +#if __riscv_xlen == 64 STR(LWU) " %[insn], (%[addr])\n" +#else + STR(LW) " %[insn], (%[addr])\n" +#endif "csrw mstatus, %[mstatus]" : [mstatus] "+&r" (__mstatus), [insn] "=&r" (val) : [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc)); @@ -86,7 +90,11 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus) asm ("csrrs %[mstatus], mstatus, %[mprv]\n" "and %[tmp], %[addr], 2\n" "bnez %[tmp], 1f\n" +#if __riscv_xlen == 64 STR(LWU) " %[insn], (%[addr])\n" +#else + STR(LW) " %[insn], (%[addr])\n" +#endif "and %[tmp], %[insn], %[rvc_mask]\n" "beq %[tmp], %[rvc_mask], 2f\n" "sll %[insn], %[insn], %[xlen_minus_16]\n" |