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authorXingyu Wu <xingyu.wu@starfivetech.com>2024-06-03 10:06:07 +0800
committerAurelien Jarno <aurelien@aurel32.net>2024-07-24 22:02:41 +0200
commitd5d0ca2bba3011ab52d19c7a50a4e032607c70bc (patch)
treea8e3c021ff7d7b17c118533a5234d2f09687dc78 /COPYING
parent0b79ea2b253ed502ccd4a734302f5577700bd253 (diff)
clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHzHEADjh7110-6.10.y
CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. But now PLL0 rate is 1GHz and the cpu frequency loads become 250/333/500/1000MHz in fact. The PLL0 rate should be default set to 1.5GHz and set the divider of cpu_core clock to 2 in safe. To keeo the cpu frequency stable when setting PLL0, the parent clock of the cpu_root clock needs to be switched from PLL0 to another parent clock and add notifier function to do this for PLL0 clock. In the function, the cpu_root clock should be operated by saving its current parent and setting a new safe parent (osc clock) before setting the PLL0 clock rate. After setting PLL0 rate, it should be switched back to the original parent clock. To keep the DTS same in Linux and U-Boot and the PLL0 rate is 1GHz in U-Boot, the PLL0 rate should be set to 1.5GHz in the driver instead of DTS. Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Message-ID: <20240603020607.25122-1-xingyu.wu@starfivetech.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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