/* * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2019 Western Digital Corporation or its affiliates. * * Authors: * Anup Patel */ #ifndef __SBI_ECALL_INTERFACE_H__ #define __SBI_ECALL_INTERFACE_H__ /* clang-format off */ /* SBI Extension IDs */ #define SBI_EXT_0_1_SET_TIMER 0x0 #define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 #define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 #define SBI_EXT_0_1_CLEAR_IPI 0x3 #define SBI_EXT_0_1_SEND_IPI 0x4 #define SBI_EXT_0_1_REMOTE_FENCE_I 0x5 #define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 #define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 #define SBI_EXT_0_1_SHUTDOWN 0x8 #define SBI_EXT_BASE 0x10 #define SBI_EXT_TIME 0x54494D45 #define SBI_EXT_IPI 0x735049 #define SBI_EXT_RFENCE 0x52464E43 #define SBI_EXT_HSM 0x48534D #define SBI_EXT_SRST 0x53525354 #define SBI_EXT_PMU 0x504D55 /* SBI function IDs for BASE extension*/ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 #define SBI_EXT_BASE_GET_IMP_ID 0x1 #define SBI_EXT_BASE_GET_IMP_VERSION 0x2 #define SBI_EXT_BASE_PROBE_EXT 0x3 #define SBI_EXT_BASE_GET_MVENDORID 0x4 #define SBI_EXT_BASE_GET_MARCHID 0x5 #define SBI_EXT_BASE_GET_MIMPID 0x6 /* SBI function IDs for TIME extension*/ #define SBI_EXT_TIME_SET_TIMER 0x0 /* SBI function IDs for IPI extension*/ #define SBI_EXT_IPI_SEND_IPI 0x0 /* SBI function IDs for RFENCE extension*/ #define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2 #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x3 #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x4 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x5 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x6 /* SBI function IDs for HSM extension */ #define SBI_EXT_HSM_HART_START 0x0 #define SBI_EXT_HSM_HART_STOP 0x1 #define SBI_EXT_HSM_HART_GET_STATUS 0x2 #define SBI_EXT_HSM_HART_SUSPEND 0x3 #define SBI_HSM_STATE_STARTED 0x0 #define SBI_HSM_STATE_STOPPED 0x1 #define SBI_HSM_STATE_START_PENDING 0x2 #define SBI_HSM_STATE_STOP_PENDING 0x3 #define SBI_HSM_STATE_SUSPENDED 0x4 #define SBI_HSM_STATE_SUSPEND_PENDING 0x5 #define SBI_HSM_STATE_RESUME_PENDING 0x6 #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 #define SBI_HSM_SUSP_PLAT_BASE 0x10000000 #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000 #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \ SBI_HSM_SUSP_PLAT_BASE) #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \ SBI_HSM_SUSP_BASE_MASK) /* SBI function IDs for SRST extension */ #define SBI_EXT_SRST_RESET 0x0 #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0 #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1 #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2 #define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT #define SBI_SRST_RESET_REASON_NONE 0x0 #define SBI_SRST_RESET_REASON_SYSFAIL 0x1 /* SBI function IDs for PMU extension */ #define SBI_EXT_PMU_NUM_COUNTERS 0x0 #define SBI_EXT_PMU_COUNTER_GET_INFO 0x1 #define SBI_EXT_PMU_COUNTER_CFG_MATCH 0x2 #define SBI_EXT_PMU_COUNTER_START 0x3 #define SBI_EXT_PMU_COUNTER_STOP 0x4 #define SBI_EXT_PMU_COUNTER_FW_READ 0x5 /** General pmu event codes specified in SBI PMU extension */ enum sbi_pmu_hw_generic_events_t { SBI_PMU_HW_NO_EVENT = 0, SBI_PMU_HW_CPU_CYCLES = 1, SBI_PMU_HW_INSTRUCTIONS = 2, SBI_PMU_HW_CACHE_REFERENCES = 3, SBI_PMU_HW_CACHE_MISSES = 4, SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, SBI_PMU_HW_BRANCH_MISSES = 6, SBI_PMU_HW_BUS_CYCLES = 7, SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, SBI_PMU_HW_REF_CPU_CYCLES = 10, SBI_PMU_HW_GENERAL_MAX, }; /** * Generalized hardware cache events: * * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x * { read, write, prefetch } x * { accesses, misses } */ enum sbi_pmu_hw_cache_id { SBI_PMU_HW_CACHE_L1D = 0, SBI_PMU_HW_CACHE_L1I = 1, SBI_PMU_HW_CACHE_LL = 2, SBI_PMU_HW_CACHE_DTLB = 3, SBI_PMU_HW_CACHE_ITLB = 4, SBI_PMU_HW_CACHE_BPU = 5, SBI_PMU_HW_CACHE_NODE = 6, SBI_PMU_HW_CACHE_MAX, }; enum sbi_pmu_hw_cache_op_id { SBI_PMU_HW_CACHE_OP_READ = 0, SBI_PMU_HW_CACHE_OP_WRITE = 1, SBI_PMU_HW_CACHE_OP_PREFETCH = 2, SBI_PMU_HW_CACHE_OP_MAX, }; enum sbi_pmu_hw_cache_op_result_id { SBI_PMU_HW_CACHE_RESULT_ACCESS = 0, SBI_PMU_HW_CACHE_RESULT_MISS = 1, SBI_PMU_HW_CACHE_RESULT_MAX, }; /** * Special "firmware" events provided by the OpenSBI, even if the hardware * does not support performance events. These events are encoded as a raw * event type in Linux kernel perf framework. */ enum sbi_pmu_fw_event_code_id { SBI_PMU_FW_MISALIGNED_LOAD = 0, SBI_PMU_FW_MISALIGNED_STORE = 1, SBI_PMU_FW_ACCESS_LOAD = 2, SBI_PMU_FW_ACCESS_STORE = 3, SBI_PMU_FW_ILLEGAL_INSN = 4, SBI_PMU_FW_SET_TIMER = 5, SBI_PMU_FW_IPI_SENT = 6, SBI_PMU_FW_IPI_RECVD = 7, SBI_PMU_FW_FENCE_I_SENT = 8, SBI_PMU_FW_FENCE_I_RECVD = 9, SBI_PMU_FW_SFENCE_VMA_SENT = 10, SBI_PMU_FW_SFENCE_VMA_RCVD = 11, SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12, SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13, SBI_PMU_FW_HFENCE_GVMA_SENT = 14, SBI_PMU_FW_HFENCE_GVMA_RCVD = 15, SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16, SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17, SBI_PMU_FW_HFENCE_VVMA_SENT = 18, SBI_PMU_FW_HFENCE_VVMA_RCVD = 19, SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21, SBI_PMU_FW_MAX, }; /** SBI PMU event idx type */ enum sbi_pmu_event_type_id { SBI_PMU_EVENT_TYPE_HW = 0x0, SBI_PMU_EVENT_TYPE_HW_CACHE = 0x1, SBI_PMU_EVENT_TYPE_HW_RAW = 0x2, SBI_PMU_EVENT_TYPE_FW = 0xf, SBI_PMU_EVENT_TYPE_MAX, }; /** SBI PMU counter type */ enum sbi_pmu_ctr_type { SBI_PMU_CTR_TYPE_HW = 0, SBI_PMU_CTR_TYPE_FW, }; /* Helper macros to decode event idx */ #define SBI_PMU_EVENT_IDX_OFFSET 20 #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF #define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000 #define SBI_PMU_EVENT_RAW_IDX 0x20000 #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF /* Flags defined for config matching function */ #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) #define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) /* Flags defined for counter start function */ #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) /* SBI base specification related macros */ #define SBI_SPEC_VERSION_MAJOR_OFFSET 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff #define SBI_EXT_VENDOR_START 0x09000000 #define SBI_EXT_VENDOR_END 0x09FFFFFF #define SBI_EXT_FIRMWARE_START 0x0A000000 #define SBI_EXT_FIRMWARE_END 0x0AFFFFFF /* SBI return error codes */ #define SBI_SUCCESS 0 #define SBI_ERR_FAILED -1 #define SBI_ERR_NOT_SUPPORTED -2 #define SBI_ERR_INVALID_PARAM -3 #define SBI_ERR_DENIED -4 #define SBI_ERR_INVALID_ADDRESS -5 #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 #define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED /* clang-format on */ #endif