From e0d1b9db8abd8288afbaa4f93a4ace6a9b6f0100 Mon Sep 17 00:00:00 2001
From: Anup Patel <anup.patel@wdc.com>
Date: Fri, 23 Jul 2021 14:09:43 +0530
Subject: lib: utils/timer: Allow separate base addresses for MTIME and
MTIMECMP
We extend the ACLINT library to support separate base addresses
for MTIME and MTIMECMP registers.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
platform/fpga/openpiton/platform.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
(limited to 'platform/fpga/openpiton/platform.c')
diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c
index 6939b57..a9bfa99 100644
--- a/platform/fpga/openpiton/platform.c
+++ b/platform/fpga/openpiton/platform.c
@@ -49,8 +49,12 @@ static struct aclint_mswi_data mswi = {
};
static struct aclint_mtimer_data mtimer = {
- .addr = OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR,
- .size = ACLINT_MTIMER_SIZE,
+ .mtime_addr = OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
+ ACLINT_DEFAULT_MTIME_OFFSET,
+ .mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
+ .mtimecmp_addr = OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
+ ACLINT_DEFAULT_MTIMECMP_OFFSET,
+ .mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
.first_hartid = 0,
.hart_count = OPENPITON_DEFAULT_HART_COUNT,
.has_64bit_mmio = TRUE,
@@ -82,7 +86,10 @@ static int openpiton_early_init(bool cold_boot)
rc = fdt_parse_compat_addr(fdt, &clint_addr, "riscv,clint0");
if (!rc) {
mswi.addr = clint_addr;
- mtimer.addr = clint_addr + CLINT_MTIMER_OFFSET;
+ mtimer.mtime_addr = clint_addr + CLINT_MTIMER_OFFSET +
+ ACLINT_DEFAULT_MTIME_OFFSET;
+ mtimer.mtimecmp_addr = clint_addr + CLINT_MTIMER_OFFSET +
+ ACLINT_DEFAULT_MTIMECMP_OFFSET;
}
return 0;
--
cgit v1.2.3