From 03ec350c83511b8ac02b23f9ee16c7ac272bf113 Mon Sep 17 00:00:00 2001 From: Shawn Chang <citypw@gmail.com> Date: Wed, 24 Apr 2019 17:44:58 +0800 Subject: docs: Add a payload section about coreboot support #116 Signed-off-by: Shawn Chang <citypw@gmail.com> --- docs/external/coreboot.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 docs/external/coreboot.md (limited to 'docs') diff --git a/docs/external/coreboot.md b/docs/external/coreboot.md new file mode 100644 index 0000000..fe2f7ba --- /dev/null +++ b/docs/external/coreboot.md @@ -0,0 +1,24 @@ +OpenSBI as coreboot payload +============================== + +[coreboot](https://www.coreboot.org/) is a free/libre and open source firmware platform support multiple hardware architectures( x86, ARMv7, arm64, PowerPC64, MIPS and RISC-V) and diverse hardware models. In RISC-V world, coreboot currently support HiFive Unleashed with OpenSBI as a payload to boot GNU/Linux: + +``` +SiFive HiFive unleashed's original firmware boot process: + +-----------+ ++------+ +------+ +------+ | BBL | +| MSEL |--->| ZSBL |--->| FSBL |--->| +-------+ ++------+ +------+ +------+ | | linux | + +---+-------+ + +coreboot boot process: + +---------------------------------------------------------------------+ + | coreboot | ++------+ +------+ | +-----------+ +----------+ +----------+ +-----------------------+ +| MSEL |-->| ZSBL |-->| | bootblock |->| romstage |->| ramstage |->| payload ( OpenSBI) | ++------+ +------+ | +-----------+ +----------+ +----------+ | +-------+ | + | | | linux | | + +---------------------------------------------+-------------+-------+-+ +``` + +The upstreaming work is still in progress. There's a [documentation](https://github.com/hardenedlinux/embedded-iot_profile/blob/master/docs/riscv/hifiveunleashed_coreboot_notes-en.md) about how to build [out-of-tree code](https://github.com/hardenedlinux/coreboot-HiFiveUnleashed) to load OpenSBI. -- cgit v1.2.3