From c0addfe751e51376a73df71336ce11826e68c939 Mon Sep 17 00:00:00 2001
From: Olof Johansson <olof@lixom.net>
Date: Sun, 3 Feb 2019 18:49:20 -0800
Subject: riscv_asm.h: Use CSR_<FOO> instead of <foo> for csr_read()
Some toolchains might not have all the CSRs available (as seen with
GCC 7.2). So, instead use the defined CSR_ values.
Signed-off-by: Olof Johansson <olof@lixom.net>
---
include/sbi/riscv_asm.h | 8 +++++---
lib/sbi_misaligned_ldst.c | 4 ++--
lib/sbi_trap.c | 8 ++++----
3 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h
index e071049..a88c086 100644
--- a/include/sbi/riscv_asm.h
+++ b/include/sbi/riscv_asm.h
@@ -10,6 +10,8 @@
#ifndef __RISCV_ASM_H__
#define __RISCV_ASM_H__
+#include <sbi/riscv_encoding.h>
+
#ifdef __ASSEMBLY__
#define __ASM_STR(x) x
#else
@@ -144,17 +146,17 @@ do { \
static inline int misa_extension(char ext)
{
- return csr_read(misa) & (1 << (ext - 'A'));
+ return csr_read(CSR_MISA) & (1 << (ext - 'A'));
}
static inline int misa_xlen(void)
{
- return ((long)csr_read(misa) < 0) ? 64 : 32;
+ return ((long)csr_read(CSR_MISA) < 0) ? 64 : 32;
}
static inline void misa_string(char *out, unsigned int out_sz)
{
- unsigned long i, val = csr_read(misa);
+ unsigned long i, val = csr_read(CSR_MISA);
for (i = 0; i < 26; i++) {
if (val & (1 << i)) {
diff --git a/lib/sbi_misaligned_ldst.c b/lib/sbi_misaligned_ldst.c
index 77885a4..8522255 100644
--- a/lib/sbi_misaligned_ldst.c
+++ b/lib/sbi_misaligned_ldst.c
@@ -28,7 +28,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
union reg_data val;
ulong mstatus = csr_read(mstatus);
ulong insn = get_insn(regs->mepc, &mstatus);
- ulong addr = csr_read(mtval);
+ ulong addr = csr_read(CSR_MTVAL);
int i, fp = 0, shift = 0, len = 0;
if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
@@ -114,7 +114,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
union reg_data val;
ulong mstatus = csr_read(mstatus);
ulong insn = get_insn(regs->mepc, &mstatus);
- ulong addr = csr_read(mtval);
+ ulong addr = csr_read(CSR_MTVAL);
int i, len = 0;
val.data_ulong = GET_RS2(insn, regs);
diff --git a/lib/sbi_trap.c b/lib/sbi_trap.c
index 4c0f2a9..fb9ca4f 100644
--- a/lib/sbi_trap.c
+++ b/lib/sbi_trap.c
@@ -89,9 +89,9 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
return SBI_ENOTSUPP;
/* Update S-mode exception info */
- csr_write(stval, tval);
- csr_write(sepc, epc);
- csr_write(scause, cause);
+ csr_write(CSR_STVAL, tval);
+ csr_write(CSR_SEPC, epc);
+ csr_write(CSR_SCAUSE, cause);
/* Set MEPC to S-mode exception vector base */
regs->mepc = csr_read(stvec);
@@ -183,6 +183,6 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
trap_error:
if (rc) {
- sbi_trap_error(msg, rc, hartid, mcause, csr_read(mtval), regs);
+ sbi_trap_error(msg, rc, hartid, mcause, csr_read(CSR_MTVAL), regs);
}
}
--
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