From 023aa6bb043420cd215379a0b31b8aceef38807b Mon Sep 17 00:00:00 2001
From: Atish Patra <atish.patra@wdc.com>
Date: Mon, 21 Jan 2019 18:17:45 -0800
Subject: lib: Do not access mi/edeleg register if S mode is not present.
As per the RISC-V ISA, mideleg and medeleg registers should not exist
if S-mode is not present for a hart.
We shouldn't access these CSRs if non S-mode harts.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
lib/sbi_hart.c | 28 +++++++++++++---------------
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/lib/sbi_hart.c b/lib/sbi_hart.c
index e12a546..7e5df72 100644
--- a/lib/sbi_hart.c
+++ b/lib/sbi_hart.c
@@ -82,21 +82,19 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
struct sbi_platform *plat = sbi_platform_ptr(scratch);
unsigned long interrupts, exceptions;
- if (!misa_extension('S')) {
- /* No delegation possible */
- interrupts = 0;
- exceptions = 0;
- } else {
- /* Send M-mode interrupts and most exceptions to S-mode */
- interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
- exceptions = (1U << CAUSE_MISALIGNED_FETCH) |
- (1U << CAUSE_BREAKPOINT) |
- (1U << CAUSE_USER_ECALL);
- if (sbi_platform_has_mfaults_delegation(plat))
- exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) |
- (1U << CAUSE_LOAD_PAGE_FAULT) |
- (1U << CAUSE_STORE_PAGE_FAULT);
- }
+ if (!misa_extension('S'))
+ /* No delegation possible as mideleg does not exist*/
+ return 0;
+
+ /* Send M-mode interrupts and most exceptions to S-mode */
+ interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
+ exceptions = (1U << CAUSE_MISALIGNED_FETCH) |
+ (1U << CAUSE_BREAKPOINT) |
+ (1U << CAUSE_USER_ECALL);
+ if (sbi_platform_has_mfaults_delegation(plat))
+ exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) |
+ (1U << CAUSE_LOAD_PAGE_FAULT) |
+ (1U << CAUSE_STORE_PAGE_FAULT);
csr_write(mideleg, interrupts);
csr_write(medeleg, exceptions);
--
cgit v1.2.3