From 3a4e1f2bd59a5185e638a2552c64344d78e0f54f Mon Sep 17 00:00:00 2001
From: NIIBE Yutaka <gniibe@fsij.org>
Date: Tue, 31 May 2016 11:49:01 +0900
Subject: Cleanup of sys and its macro
---
mcu/ABOUT-SYS | 51 +++++
mcu/adc-stm32f103.c | 2 +-
mcu/clk_gpio_init-stm32.c | 368 ++++++++++++++++++++++++++++++++++++
mcu/clk_gpio_init-stm32f103.c | 368 ------------------------------------
mcu/sys-mkl27z.h | 38 ++--
mcu/sys-stm32f030.c | 421 ++++++++++++++++++++++++++++++++++++++++++
mcu/sys-stm32f030.h | 134 ++++++++++++++
mcu/sys-stm32f103.c | 2 +-
mcu/sys-stm32f103.h | 16 +-
9 files changed, 1001 insertions(+), 399 deletions(-)
create mode 100644 mcu/clk_gpio_init-stm32.c
delete mode 100644 mcu/clk_gpio_init-stm32f103.c
create mode 100644 mcu/sys-stm32f030.c
create mode 100644 mcu/sys-stm32f030.h
(limited to 'mcu')
diff --git a/mcu/ABOUT-SYS b/mcu/ABOUT-SYS
index c5a7490..d285c88 100644
--- a/mcu/ABOUT-SYS
+++ b/mcu/ABOUT-SYS
@@ -4,6 +4,49 @@ Consideration about SYS and the first pages of flash ROM
Now, I'm developing something like SYS for Kinetis L MCU, so, I write
this document.
+* Compatibility
+
+ SYS 1.0: The first verson
+ SYS 2.0: Added clock_init, gpio_init
+ SYS 2.1: Added sys_board_id, sys_board_name
+ SYS 3.0: Don't setup NVIC priority by usb_lld_sys_init
+
+
+* Macro definition by DEFS in Makefile
+
+ - USE_SYS_CLOCK_GPIO_SETTING
+
+ Define this macro to ask chopstx/entry.c (the runtime code before
+ MAIN function) to use function entries in SYS for clock_init and
+ gpio_init.
+
+ If not defined, entry.c includes the code for clock_init and
+ gpio_init which might be different to a board, and use them (entries
+ in SYS will not be used). This works well with the ROM of SYS
+ 1.0.
+
+ Note that SYS entries of clock_init and gpio_init were introduced
+ in SYS 2.0. So, enable this macro only if the ROM is SYS 2.0 or
+ later.
+
+ - USE_SYS_BOARD_ID
+
+ Define this macro in a driver to get "sys_board_id" in SYS, so
+ that the driver can support various boards at runtime by changing
+ the settings according to the board.
+
+ A simple driver could only support a single board, by the compile
+ time (BOARD_ID in board-*.h) choice of of a settings.
+
+ Note that SYS entries of sys_board_id and sys_board_name were
+ introduced in SYS 2.1. So, enable this macro only if the ROM is
+ SYS 2.1 or later.
+
+ - USE_SYS3
+
+ By defining this, it will have same effect of defining both of
+ USE_SYS_CLOCK_GPIO_SETTING and USE_SYS_BOARD_ID internally.
+
About SYS on STM32F103
======================
@@ -185,4 +228,12 @@ Three pages (3KiB) usage:
+An Example of No-use of SYS
+===========================
+
+See example-fsm-55 for an example of no use of SYS.
+
+While chopstx/entry.c defines vectors in ROM and RAM, those are simply
+discarded by example-fsm-55/hacker-emblem.ld.
+
--
diff --git a/mcu/adc-stm32f103.c b/mcu/adc-stm32f103.c
index 2ff852b..fd40312 100644
--- a/mcu/adc-stm32f103.c
+++ b/mcu/adc-stm32f103.c
@@ -132,8 +132,8 @@ adc_init (void)
}
#include "board.h"
+#if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)
#include "mcu/sys-stm32f103.h"
-#if defined(HAVE_SYS_H)
# define SYS_BOARD_ID sys_board_id
#else
# define SYS_BOARD_ID BOARD_ID
diff --git a/mcu/clk_gpio_init-stm32.c b/mcu/clk_gpio_init-stm32.c
new file mode 100644
index 0000000..ec94932
--- /dev/null
+++ b/mcu/clk_gpio_init-stm32.c
@@ -0,0 +1,368 @@
+/*
+ * clk_gpio_init-stm32.c - Clock and GPIO initialization for STM32.
+ *
+ * Copyright (C) 2015 Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#define STM32_SW_HSI (0 << 0)
+#define STM32_SW_PLL (2 << 0)
+#define STM32_PLLSRC_HSI (0 << 16)
+#define STM32_PLLSRC_HSE (1 << 16)
+
+#define STM32_PLLXTPRE_DIV1 (0 << 17)
+#define STM32_PLLXTPRE_DIV2 (1 << 17)
+
+#define STM32_HPRE_DIV1 (0 << 4)
+
+#define STM32_PPRE1_DIV1 (0 << 8)
+#define STM32_PPRE1_DIV2 (4 << 8)
+
+#define STM32_PPRE2_DIV1 (0 << 11)
+#define STM32_PPRE2_DIV2 (4 << 11)
+
+#define STM32_ADCPRE_DIV4 (1 << 14)
+#define STM32_ADCPRE_DIV6 (2 << 14)
+
+#define STM32_USBPRE_DIV1P5 (0 << 22)
+
+#define STM32_MCO_NOCLOCK (0 << 24)
+
+#if defined(MCU_STM32F0)
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#define STM32_PLLSRC STM32_PLLSRC_HSI
+#define STM32_FLASHBITS 0x00000011
+#define STM32_PLLCLKIN (STM32_HSICLK / 2)
+#else
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_FLASHBITS 0x00000012
+#define STM32_PLLCLKIN (STM32_HSECLK / 1)
+#endif
+
+#define STM32_SW STM32_SW_PLL
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#define STM32_ADCPRE STM32_ADCPRE_DIV6
+#define STM32_MCOSEL STM32_MCO_NOCLOCK
+#define STM32_USBPRE STM32_USBPRE_DIV1P5
+
+#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
+#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+#define STM32_SYSCLK STM32_PLLCLKOUT
+#define STM32_HCLK (STM32_SYSCLK / 1)
+
+
+#define PERIPH_BASE 0x40000000
+#define APBPERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+struct RCC {
+ volatile uint32_t CR;
+ volatile uint32_t CFGR;
+ volatile uint32_t CIR;
+ volatile uint32_t APB2RSTR;
+ volatile uint32_t APB1RSTR;
+ volatile uint32_t AHBENR;
+ volatile uint32_t APB2ENR;
+ volatile uint32_t APB1ENR;
+ volatile uint32_t BDCR;
+ volatile uint32_t CSR;
+#if defined(MCU_STM32F0)
+ volatile uint32_t AHBRSTR;
+ volatile uint32_t CFGR2;
+ volatile uint32_t CFGR3;
+ volatile uint32_t CR2;
+#endif
+};
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
+
+#define RCC_APB1ENR_USBEN 0x00800000
+#define RCC_APB1RSTR_USBRST 0x00800000
+
+#define RCC_CR_HSION 0x00000001
+#define RCC_CR_HSIRDY 0x00000002
+#define RCC_CR_HSITRIM 0x000000F8
+#define RCC_CR_HSEON 0x00010000
+#define RCC_CR_HSERDY 0x00020000
+#define RCC_CR_PLLON 0x01000000
+#define RCC_CR_PLLRDY 0x02000000
+
+#define RCC_CFGR_SWS 0x0000000C
+#define RCC_CFGR_SWS_HSI 0x00000000
+
+#define RCC_AHBENR_CRCEN 0x0040
+
+#if defined(MCU_STM32F0)
+#define RCC_AHBRSTR_IOPARST 0x00020000
+#define RCC_AHBRSTR_IOPBRST 0x00040000
+#define RCC_AHBRSTR_IOPCRST 0x00080000
+#define RCC_AHBRSTR_IOPDRST 0x00100000
+#define RCC_AHBRSTR_IOPFRST 0x00400000
+
+#define RCC_AHBENR_IOPAEN 0x00020000
+#define RCC_AHBENR_IOPBEN 0x00040000
+#define RCC_AHBENR_IOPCEN 0x00080000
+#define RCC_AHBENR_IOPDEN 0x00100000
+#define RCC_AHBENR_IOPFEN 0x00400000
+
+#define RCC_APB2RSTR_SYSCFGRST 0x00000001
+#define RCC_APB2ENR_SYSCFGEN 0x00000001
+#else
+#define RCC_APB2RSTR_AFIORST 0x00000001
+#define RCC_APB2RSTR_IOPARST 0x00000004
+#define RCC_APB2RSTR_IOPBRST 0x00000008
+#define RCC_APB2RSTR_IOPCRST 0x00000010
+#define RCC_APB2RSTR_IOPDRST 0x00000020
+#define RCC_APB2RSTR_IOPERST 0x00000040
+#define RCC_APB2RSTR_IOPFRST 0x00000080
+#define RCC_APB2RSTR_IOPGRST 0x00000100
+
+#define RCC_APB2ENR_AFIOEN 0x00000001
+#define RCC_APB2ENR_IOPAEN 0x00000004
+#define RCC_APB2ENR_IOPBEN 0x00000008
+#define RCC_APB2ENR_IOPCEN 0x00000010
+#define RCC_APB2ENR_IOPDEN 0x00000020
+#define RCC_APB2ENR_IOPEEN 0x00000040
+#define RCC_APB2ENR_IOPFEN 0x00000080
+#define RCC_APB2ENR_IOPGEN 0x00000100
+#endif
+
+#if defined(MCU_STM32F0)
+struct SYSCFG {
+ volatile uint32_t CFGR1;
+ uint32_t dummy0;
+ volatile uint32_t EXTICR[4];
+ volatile uint32_t CFGR2;
+};
+#define SYSCFG_CFGR1_MEM_MODE 0x03
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
+#endif
+
+struct FLASH {
+ volatile uint32_t ACR;
+ volatile uint32_t KEYR;
+ volatile uint32_t OPTKEYR;
+ volatile uint32_t SR;
+ volatile uint32_t CR;
+ volatile uint32_t AR;
+ volatile uint32_t RESERVED;
+ volatile uint32_t OBR;
+ volatile uint32_t WRPR;
+};
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
+static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
+
+static void __attribute__((used))
+clock_init (void)
+{
+ /* HSI setup */
+ RCC->CR |= RCC_CR_HSION;
+ while (!(RCC->CR & RCC_CR_HSIRDY))
+ ;
+ /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
+ RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
+ RCC->CFGR = 0;
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ ;
+
+#if !defined(MCU_STM32F0)
+ /* HSE setup */
+ RCC->CR |= RCC_CR_HSEON;
+ while (!(RCC->CR & RCC_CR_HSERDY))
+ ;
+#endif
+
+ /* PLL setup */
+ RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ;
+
+ /* Clock settings */
+ RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
+ | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+ /*
+ * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
+ */
+
+ /* Flash setup */
+ FLASH->ACR = STM32_FLASHBITS;
+
+ /* CRC */
+ RCC->AHBENR |= RCC_AHBENR_CRCEN;
+
+ /* Switching on the configured clock source. */
+ RCC->CFGR |= STM32_SW;
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+
+#if defined(MCU_STM32F0)
+ RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+ RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
+ RCC->APB2RSTR = 0;
+
+# if defined(REQUIRE_CLOCK_GPIO_SETTING_IN_SYS)
+ /* Use vectors on RAM */
+ SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
+# endif
+#endif
+}
+
+
+#if defined(MCU_STM32F0)
+struct GPIO {
+ volatile uint32_t MODER;
+ volatile uint16_t OTYPER;
+ uint16_t dummy0;
+ volatile uint32_t OSPEEDR;
+ volatile uint32_t PUPDR;
+ volatile uint16_t IDR;
+ uint16_t dummy1;
+ volatile uint16_t ODR;
+ uint16_t dummy2;
+ volatile uint16_t BSRR;
+ uint16_t dummy3;
+ volatile uint32_t LCKR;
+ volatile uint32_t AFR[2];
+ volatile uint16_t BRR;
+ uint16_t dummy4;
+};
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
+#define GPIOA ((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
+#define GPIOB ((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
+#define GPIOC ((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
+#define GPIOD ((struct GPIO *) GPIOD_BASE)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
+#define GPIOF ((struct GPIO *) GPIOF_BASE)
+#else
+struct AFIO
+{
+ volatile uint32_t EVCR;
+ volatile uint32_t MAPR;
+ volatile uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ volatile uint32_t MAPR2;
+};
+
+#define AFIO_BASE 0x40010000
+static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
+
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE 0x02000000
+
+
+struct GPIO {
+ volatile uint32_t CRL;
+ volatile uint32_t CRH;
+ volatile uint32_t IDR;
+ volatile uint32_t ODR;
+ volatile uint32_t BSRR;
+ volatile uint32_t BRR;
+ volatile uint32_t LCKR;
+};
+
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOA ((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOB ((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOC ((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOD ((struct GPIO *) GPIOD_BASE)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOE ((struct GPIO *) GPIOE_BASE)
+#endif
+
+static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
+#ifdef GPIO_USB_BASE
+static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
+#endif
+#ifdef GPIO_OTHER_BASE
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
+#endif
+
+static void __attribute__((used))
+gpio_init (void)
+{
+ /* Enable GPIO clock. */
+#if defined(MCU_STM32F0)
+ RCC->AHBENR |= RCC_ENR_IOP_EN;
+ RCC->AHBRSTR = RCC_RSTR_IOP_RST;
+ RCC->AHBRSTR = 0;
+#else
+ RCC->APB2ENR |= RCC_ENR_IOP_EN;
+ RCC->APB2RSTR = RCC_RSTR_IOP_RST;
+ RCC->APB2RSTR = 0;
+#endif
+
+#if defined(MCU_STM32F0)
+ GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
+ GPIO_LED->OTYPER = VAL_GPIO_LED_OTYPER;
+ GPIO_LED->MODER = VAL_GPIO_LED_MODER;
+ GPIO_LED->PUPDR = VAL_GPIO_LED_PUPDR;
+
+#ifdef GPIO_OTHER_BASE
+ GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
+ GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
+ GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
+ GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
+#endif
+#else
+#ifdef AFIO_MAPR_SOMETHING
+ AFIO->MAPR |= AFIO_MAPR_SOMETHING;
+#endif
+
+ /* LED is mandatory. If it's on an independent port, we configure it. */
+ GPIO_LED->ODR = VAL_GPIO_LED_ODR;
+ GPIO_LED->CRH = VAL_GPIO_LED_CRH;
+ GPIO_LED->CRL = VAL_GPIO_LED_CRL;
+
+ /* If there is USB enabler pin and it's independent, we configure it. */
+#if defined(GPIO_USB_BASE) && GPIO_USB_BASE != GPIO_LED_BASE
+ GPIO_USB->ODR = VAL_GPIO_USB_ODR;
+ GPIO_USB->CRH = VAL_GPIO_USB_CRH;
+ GPIO_USB->CRL = VAL_GPIO_USB_CRL;
+#endif
+
+#ifdef GPIO_OTHER_BASE
+ GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
+ GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
+ GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
+#endif
+#endif
+}
diff --git a/mcu/clk_gpio_init-stm32f103.c b/mcu/clk_gpio_init-stm32f103.c
deleted file mode 100644
index 50660ea..0000000
--- a/mcu/clk_gpio_init-stm32f103.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * clk_gpio_init-stm32.c - Clock and GPIO initialization for STM32.
- *
- * Copyright (C) 2015 Flying Stone Technology
- * Author: NIIBE Yutaka <gniibe@fsij.org>
- *
- * This file is a part of Chopstx, a thread library for embedded.
- *
- * Chopstx is free software: you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * Chopstx is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- *
- * As additional permission under GNU GPL version 3 section 7, you may
- * distribute non-source form of the Program without the copy of the
- * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
- *
- */
-
-#define STM32_SW_HSI (0 << 0)
-#define STM32_SW_PLL (2 << 0)
-#define STM32_PLLSRC_HSI (0 << 16)
-#define STM32_PLLSRC_HSE (1 << 16)
-
-#define STM32_PLLXTPRE_DIV1 (0 << 17)
-#define STM32_PLLXTPRE_DIV2 (1 << 17)
-
-#define STM32_HPRE_DIV1 (0 << 4)
-
-#define STM32_PPRE1_DIV1 (0 << 8)
-#define STM32_PPRE1_DIV2 (4 << 8)
-
-#define STM32_PPRE2_DIV1 (0 << 11)
-#define STM32_PPRE2_DIV2 (4 << 11)
-
-#define STM32_ADCPRE_DIV4 (1 << 14)
-#define STM32_ADCPRE_DIV6 (2 << 14)
-
-#define STM32_USBPRE_DIV1P5 (0 << 22)
-
-#define STM32_MCO_NOCLOCK (0 << 24)
-
-#if defined(MCU_STM32F0)
-#define STM32_PPRE1 STM32_PPRE1_DIV1
-#define STM32_PLLSRC STM32_PLLSRC_HSI
-#define STM32_FLASHBITS 0x00000011
-#define STM32_PLLCLKIN (STM32_HSICLK / 2)
-#else
-#define STM32_PPRE1 STM32_PPRE1_DIV2
-#define STM32_PLLSRC STM32_PLLSRC_HSE
-#define STM32_FLASHBITS 0x00000012
-#define STM32_PLLCLKIN (STM32_HSECLK / 1)
-#endif
-
-#define STM32_SW STM32_SW_PLL
-#define STM32_HPRE STM32_HPRE_DIV1
-#define STM32_PPRE2 STM32_PPRE2_DIV1
-#define STM32_ADCPRE STM32_ADCPRE_DIV6
-#define STM32_MCOSEL STM32_MCO_NOCLOCK
-#define STM32_USBPRE STM32_USBPRE_DIV1P5
-
-#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK STM32_PLLCLKOUT
-#define STM32_HCLK (STM32_SYSCLK / 1)
-
-
-#define PERIPH_BASE 0x40000000
-#define APBPERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
-
-struct RCC {
- volatile uint32_t CR;
- volatile uint32_t CFGR;
- volatile uint32_t CIR;
- volatile uint32_t APB2RSTR;
- volatile uint32_t APB1RSTR;
- volatile uint32_t AHBENR;
- volatile uint32_t APB2ENR;
- volatile uint32_t APB1ENR;
- volatile uint32_t BDCR;
- volatile uint32_t CSR;
-#if defined(MCU_STM32F0)
- volatile uint32_t AHBRSTR;
- volatile uint32_t CFGR2;
- volatile uint32_t CFGR3;
- volatile uint32_t CR2;
-#endif
-};
-
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN 0x00800000
-#define RCC_APB1RSTR_USBRST 0x00800000
-
-#define RCC_CR_HSION 0x00000001
-#define RCC_CR_HSIRDY 0x00000002
-#define RCC_CR_HSITRIM 0x000000F8
-#define RCC_CR_HSEON 0x00010000
-#define RCC_CR_HSERDY 0x00020000
-#define RCC_CR_PLLON 0x01000000
-#define RCC_CR_PLLRDY 0x02000000
-
-#define RCC_CFGR_SWS 0x0000000C
-#define RCC_CFGR_SWS_HSI 0x00000000
-
-#define RCC_AHBENR_CRCEN 0x0040
-
-#if defined(MCU_STM32F0)
-#define RCC_AHBRSTR_IOPARST 0x00020000
-#define RCC_AHBRSTR_IOPBRST 0x00040000
-#define RCC_AHBRSTR_IOPCRST 0x00080000
-#define RCC_AHBRSTR_IOPDRST 0x00100000
-#define RCC_AHBRSTR_IOPFRST 0x00400000
-
-#define RCC_AHBENR_IOPAEN 0x00020000
-#define RCC_AHBENR_IOPBEN 0x00040000
-#define RCC_AHBENR_IOPCEN 0x00080000
-#define RCC_AHBENR_IOPDEN 0x00100000
-#define RCC_AHBENR_IOPFEN 0x00400000
-
-#define RCC_APB2RSTR_SYSCFGRST 0x00000001
-#define RCC_APB2ENR_SYSCFGEN 0x00000001
-#else
-#define RCC_APB2RSTR_AFIORST 0x00000001
-#define RCC_APB2RSTR_IOPARST 0x00000004
-#define RCC_APB2RSTR_IOPBRST 0x00000008
-#define RCC_APB2RSTR_IOPCRST 0x00000010
-#define RCC_APB2RSTR_IOPDRST 0x00000020
-#define RCC_APB2RSTR_IOPERST 0x00000040
-#define RCC_APB2RSTR_IOPFRST 0x00000080
-#define RCC_APB2RSTR_IOPGRST 0x00000100
-
-#define RCC_APB2ENR_AFIOEN 0x00000001
-#define RCC_APB2ENR_IOPAEN 0x00000004
-#define RCC_APB2ENR_IOPBEN 0x00000008
-#define RCC_APB2ENR_IOPCEN 0x00000010
-#define RCC_APB2ENR_IOPDEN 0x00000020
-#define RCC_APB2ENR_IOPEEN 0x00000040
-#define RCC_APB2ENR_IOPFEN 0x00000080
-#define RCC_APB2ENR_IOPGEN 0x00000100
-#endif
-
-#if defined(MCU_STM32F0)
-struct SYSCFG {
- volatile uint32_t CFGR1;
- uint32_t dummy0;
- volatile uint32_t EXTICR[4];
- volatile uint32_t CFGR2;
-};
-#define SYSCFG_CFGR1_MEM_MODE 0x03
-
-#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
-static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
-#endif
-
-struct FLASH {
- volatile uint32_t ACR;
- volatile uint32_t KEYR;
- volatile uint32_t OPTKEYR;
- volatile uint32_t SR;
- volatile uint32_t CR;
- volatile uint32_t AR;
- volatile uint32_t RESERVED;
- volatile uint32_t OBR;
- volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void __attribute__((used))
-clock_init (void)
-{
- /* HSI setup */
- RCC->CR |= RCC_CR_HSION;
- while (!(RCC->CR & RCC_CR_HSIRDY))
- ;
- /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
- RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
- RCC->CFGR = 0;
- while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
- ;
-
-#if !defined(MCU_STM32F0)
- /* HSE setup */
- RCC->CR |= RCC_CR_HSEON;
- while (!(RCC->CR & RCC_CR_HSERDY))
- ;
-#endif
-
- /* PLL setup */
- RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
- RCC->CR |= RCC_CR_PLLON;
- while (!(RCC->CR & RCC_CR_PLLRDY))
- ;
-
- /* Clock settings */
- RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
- | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
- /*
- * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
- */
-
- /* Flash setup */
- FLASH->ACR = STM32_FLASHBITS;
-
- /* CRC */
- RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
- /* Switching on the configured clock source. */
- RCC->CFGR |= STM32_SW;
- while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
- ;
-
-#if defined(MCU_STM32F0)
- RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
- RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
- RCC->APB2RSTR = 0;
-
-# if defined(HAVE_SYS_H)
- /* Use vectors on RAM */
- SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
-# endif
-#endif
-}
-
-
-#if defined(MCU_STM32F0)
-struct GPIO {
- volatile uint32_t MODER;
- volatile uint16_t OTYPER;
- uint16_t dummy0;
- volatile uint32_t OSPEEDR;
- volatile uint32_t PUPDR;
- volatile uint16_t IDR;
- uint16_t dummy1;
- volatile uint16_t ODR;
- uint16_t dummy2;
- volatile uint16_t BSRR;
- uint16_t dummy3;
- volatile uint32_t LCKR;
- volatile uint32_t AFR[2];
- volatile uint16_t BRR;
- uint16_t dummy4;
-};
-
-#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
-#define GPIOA ((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
-#define GPIOB ((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
-#define GPIOC ((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
-#define GPIOD ((struct GPIO *) GPIOD_BASE)
-#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
-#define GPIOF ((struct GPIO *) GPIOF_BASE)
-#else
-struct AFIO
-{
- volatile uint32_t EVCR;
- volatile uint32_t MAPR;
- volatile uint32_t EXTICR[4];
- uint32_t RESERVED0;
- volatile uint32_t MAPR2;
-};
-
-#define AFIO_BASE 0x40010000
-static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
-
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
-#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE 0x02000000
-
-
-struct GPIO {
- volatile uint32_t CRL;
- volatile uint32_t CRH;
- volatile uint32_t IDR;
- volatile uint32_t ODR;
- volatile uint32_t BSRR;
- volatile uint32_t BRR;
- volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOA ((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOB ((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOC ((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOD ((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOE ((struct GPIO *) GPIOE_BASE)
-#endif
-
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-#ifdef GPIO_USB_BASE
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-#endif
-#ifdef GPIO_OTHER_BASE
-static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
-#endif
-
-static void __attribute__((used))
-gpio_init (void)
-{
- /* Enable GPIO clock. */
-#if defined(MCU_STM32F0)
- RCC->AHBENR |= RCC_ENR_IOP_EN;
- RCC->AHBRSTR = RCC_RSTR_IOP_RST;
- RCC->AHBRSTR = 0;
-#else
- RCC->APB2ENR |= RCC_ENR_IOP_EN;
- RCC->APB2RSTR = RCC_RSTR_IOP_RST;
- RCC->APB2RSTR = 0;
-#endif
-
-#if defined(MCU_STM32F0)
- GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
- GPIO_LED->OTYPER = VAL_GPIO_LED_OTYPER;
- GPIO_LED->MODER = VAL_GPIO_LED_MODER;
- GPIO_LED->PUPDR = VAL_GPIO_LED_PUPDR;
-
-#ifdef GPIO_OTHER_BASE
- GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
- GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
- GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
- GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
-#endif
-#else
-#ifdef AFIO_MAPR_SOMETHING
- AFIO->MAPR |= AFIO_MAPR_SOMETHING;
-#endif
-
- /* LED is mandatory. If it's on an independent port, we configure it. */
- GPIO_LED->ODR = VAL_GPIO_LED_ODR;
- GPIO_LED->CRH = VAL_GPIO_LED_CRH;
- GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-
- /* If there is USB enabler pin and it's independent, we configure it. */
-#if defined(GPIO_USB_BASE) && GPIO_USB_BASE != GPIO_LED_BASE
- GPIO_USB->ODR = VAL_GPIO_USB_ODR;
- GPIO_USB->CRH = VAL_GPIO_USB_CRH;
- GPIO_USB->CRL = VAL_GPIO_USB_CRL;
-#endif
-
-#ifdef GPIO_OTHER_BASE
- GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
- GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
- GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
-#endif
-#endif
-}
diff --git a/mcu/sys-mkl27z.h b/mcu/sys-mkl27z.h
index eed5d92..855cc62 100644
--- a/mcu/sys-mkl27z.h
+++ b/mcu/sys-mkl27z.h
@@ -1,30 +1,12 @@
extern const uint8_t sys_version[8];
+#if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)
extern const uint32_t sys_board_id;
extern const char *const sys_board_name;
+#endif
typedef void (*handler)(void);
extern handler sys_vector[16];
-/*
- * Users can override INLINE by 'attribute((used))' to have an
- * implementation defined.
- */
-#if !defined(INLINE)
-#define INLINE __inline__
-#endif
-
-static INLINE void
-clock_init (void)
-{
- (*sys_vector[0]) ();
-}
-
-static INLINE void
-gpio_init (void)
-{
- (*sys_vector[1]) ();
-}
-
static inline void
set_led (int on)
{
@@ -39,3 +21,19 @@ void crc32_u32 (unsigned int *, unsigned int);
int flash_erase_page (uint32_t addr);
int flash_program_word (uint32_t addr, uint32_t word);
+
+#ifdef REQUIRE_CLOCK_GPIO_SETTING_IN_SYS
+/* Provide the function entries. */
+
+static void __attribute__ ((used))
+clock_init (void)
+{
+ (*sys_vector[0]) ();
+}
+
+static void __attribute__ ((used))
+gpio_init (void)
+{
+ (*sys_vector[1]) ();
+}
+#endif
diff --git a/mcu/sys-stm32f030.c b/mcu/sys-stm32f030.c
new file mode 100644
index 0000000..04090d2
--- /dev/null
+++ b/mcu/sys-stm32f030.c
@@ -0,0 +1,421 @@
+/*
+ * sys.c - system routines for the initial page for STM32F030 / STM32F103.
+ *
+ * Copyright (C) 2013, 2014, 2015, 2016 Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * Copying and distribution of this file, with or without modification,
+ * are permitted in any medium without royalty provided the copyright
+ * notice and this notice are preserved. This file is offered as-is,
+ * without any warranty.
+ *
+ * When the flash ROM is protected, we cannot modify the initial page.
+ * We put some system routines (which is useful for any program) here.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "board.h"
+
+#include "mcu/clk_gpio_init-stm32.c"
+
+
+static void
+usb_cable_config (int enable)
+{
+#if defined(GPIO_USB_SET_TO_ENABLE)
+ if (enable)
+ GPIO_USB->BSRR = (1 << GPIO_USB_SET_TO_ENABLE);
+ else
+ GPIO_USB->BRR = (1 << GPIO_USB_SET_TO_ENABLE);
+#elif defined(GPIO_USB_CLEAR_TO_ENABLE)
+ if (enable)
+ GPIO_USB->BRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
+ else
+ GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
+#else
+ (void)enable;
+#endif
+}
+
+void
+set_led (int on)
+{
+#if defined(GPIO_LED_CLEAR_TO_EMIT)
+ if (on)
+ GPIO_LED->BRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
+ else
+ GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
+#else
+ if (on)
+ GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT);
+ else
+ GPIO_LED->BRR = (1 << GPIO_LED_SET_TO_EMIT);
+#endif
+}
+
+static void wait (int count)
+{
+ int i;
+
+ for (i = 0; i < count; i++)
+ asm volatile ("" : : "r" (i) : "memory");
+}
+
+
+static void
+usb_lld_sys_shutdown (void)
+{
+ RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
+ RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
+ usb_cable_config (0);
+}
+
+static void
+usb_lld_sys_init (void)
+{
+ if ((RCC->APB1ENR & RCC_APB1ENR_USBEN)
+ && (RCC->APB1RSTR & RCC_APB1RSTR_USBRST) == 0)
+ /* Make sure the device is disconnected, even after core reset. */
+ {
+ usb_lld_sys_shutdown ();
+ /* Disconnect requires SE0 (>= 2.5uS). */
+ wait (300);
+ }
+
+ usb_cable_config (1);
+ RCC->APB1ENR |= RCC_APB1ENR_USBEN;
+ RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
+ RCC->APB1RSTR = 0;
+}
+
+#define FLASH_KEY1 0x45670123UL
+#define FLASH_KEY2 0xCDEF89ABUL
+
+enum flash_status
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_PG,
+ FLASH_ERROR_WRP,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+};
+
+static void __attribute__ ((used))
+flash_unlock (void)
+{
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+
+#define intr_disable() asm volatile ("cpsid i" : : : "memory")
+#define intr_enable() asm volatile ("cpsie i" : : : "memory")
+
+#define FLASH_SR_BSY 0x01
+#define FLASH_SR_PGERR 0x04
+#define FLASH_SR_WRPRTERR 0x10
+#define FLASH_SR_EOP 0x20
+
+#define FLASH_CR_PG 0x0001
+#define FLASH_CR_PER 0x0002
+#define FLASH_CR_MER 0x0004
+#define FLASH_CR_OPTPG 0x0010
+#define FLASH_CR_OPTER 0x0020
+#define FLASH_CR_STRT 0x0040
+#define FLASH_CR_LOCK 0x0080
+#define FLASH_CR_OPTWRE 0x0200
+#define FLASH_CR_ERRIE 0x0400
+#define FLASH_CR_EOPIE 0x1000
+
+static int
+flash_wait_for_last_operation (uint32_t timeout)
+{
+ int status;
+
+ do
+ {
+ status = FLASH->SR;
+ if (--timeout == 0)
+ break;
+ }
+ while ((status & FLASH_SR_BSY) != 0);
+
+ return status & (FLASH_SR_BSY|FLASH_SR_PGERR|FLASH_SR_WRPRTERR);
+}
+
+#define FLASH_PROGRAM_TIMEOUT 0x00010000
+#define FLASH_ERASE_TIMEOUT 0x01000000
+
+static int
+flash_program_halfword (uint32_t addr, uint16_t data)
+{
+ int status;
+
+ status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
+
+ intr_disable ();
+ if (status == 0)
+ {
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(volatile uint16_t *)addr = data;
+
+ status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
+ FLASH->CR &= ~FLASH_CR_PG;
+ }
+ intr_enable ();
+
+ return status;
+}
+
+static int
+flash_erase_page (uint32_t addr)
+{
+ int status;
+
+ status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
+
+ intr_disable ();
+ if (status == 0)
+ {
+ FLASH->CR |= FLASH_CR_PER;
+ FLASH->AR = addr;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
+ FLASH->CR &= ~FLASH_CR_PER;
+ }
+ intr_enable ();
+
+ return status;
+}
+
+static int
+flash_check_blank (const uint8_t *p_start, size_t size)
+{
+ const uint8_t *p;
+
+ for (p = p_start; p < p_start + size; p++)
+ if (*p != 0xff)
+ return 0;
+
+ return 1;
+}
+
+#define FLASH_START_ADDR 0x08000000 /* Fixed for all STM32F0/F1. */
+#define FLASH_OFFSET 0x1000 /* First pages are not-writable
+ when protected. */
+#if defined(__ARM_ARCH_6M__)
+#define FLASH_SIZE_REG ((uint16_t *)0x1ffff7cc)
+#define CHIP_ID_REG ((uint32_t *)0x40015800)
+#else
+#define FLASH_SIZE_REG ((uint16_t *)0x1ffff7e0)
+#define CHIP_ID_REG ((uint32_t *)0xe0042000)
+#endif
+#define FLASH_START (FLASH_START_ADDR+FLASH_OFFSET)
+
+static int
+flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
+{
+ int status;
+ uint32_t flash_end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
+
+ if (dst_addr < FLASH_START || dst_addr + len > flash_end)
+ return 0;
+
+ while (len)
+ {
+ uint16_t hw = *src++;
+
+ hw |= (*src++ << 8);
+ status = flash_program_halfword (dst_addr, hw);
+ if (status != 0)
+ return 0; /* error return */
+
+ dst_addr += 2;
+ len -= 2;
+ }
+
+ return 1;
+}
+
+#define OPTION_BYTES_ADDR 0x1ffff800
+
+static int
+flash_protect (void)
+{
+ int status;
+ uint32_t option_bytes_value;
+
+ status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
+
+ intr_disable ();
+ if (status == 0)
+ {
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ FLASH->CR |= FLASH_CR_OPTER;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
+ FLASH->CR &= ~FLASH_CR_OPTER;
+ }
+ intr_enable ();
+
+ if (status != 0)
+ return 0;
+
+ option_bytes_value = *(uint32_t *)OPTION_BYTES_ADDR;
+ return (option_bytes_value & 0xff) == 0xff ? 1 : 0;
+}
+
+static void __attribute__((naked))
+flash_erase_all_and_exec (void (*entry)(void))
+{
+ uint32_t addr = FLASH_START;
+ uint32_t end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
+ uint32_t page_size = 1024;
+ int r;
+
+ if (((*CHIP_ID_REG) & 0xfff) == 0x0414)
+ page_size = 2048;
+
+ while (addr < end)
+ {
+ r = flash_erase_page (addr);
+ if (r != 0)
+ break;
+
+ addr += page_size;
+ }
+
+ if (addr >= end)
+ (*entry) ();
+
+ for (;;);
+}
+
+struct SCB
+{
+ volatile uint32_t CPUID;
+ volatile uint32_t ICSR;
+ volatile uint32_t VTOR;
+ volatile uint32_t AIRCR;
+ volatile uint32_t SCR;
+ volatile uint32_t CCR;
+ volatile uint8_t SHP[12];
+ volatile uint32_t SHCSR;
+ volatile uint32_t CFSR;
+ volatile uint32_t HFSR;
+ volatile uint32_t DFSR;
+ volatile uint32_t MMFAR;
+ volatile uint32_t BFAR;
+ volatile uint32_t AFSR;
+ volatile uint32_t PFR[2];
+ volatile uint32_t DFR;
+ volatile uint32_t ADR;
+ volatile uint32_t MMFR[4];
+ volatile uint32_t ISAR[5];
+};
+
+#define SCS_BASE (0xE000E000)
+#define SCB_BASE (SCS_BASE + 0x0D00)
+static struct SCB *const SCB = ((struct SCB *const) SCB_BASE);
+
+#define SYSRESETREQ 0x04
+static void
+nvic_system_reset (void)
+{
+ SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
+ asm volatile ("dsb");
+ for (;;);
+}
+
+static void __attribute__ ((naked))
+reset (void)
+{
+ /*
+ * This code may not be at the start of flash ROM, because of DFU.
+ * So, we take the address from PC.
+ */
+#if defined(__ARM_ARCH_6M__)
+ asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
+ "ldr r0, 1f\n\t" /* r0 = RAM start */
+ "mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */
+ "mov r2, #0x10\n\t"
+ "lsl r2, #8\n\t"
+ "add r1, r1, r2\n\t"
+ "sub r2, r2, #1\n\t"
+ "bic r1, r1, r2\n\t"
+ "mov r2, #188\n"
+ "2:\n\t" /* Copy vectors. It will be enabled later by clock_init. */
+ "ldr r3, [r1, r2]\n\t"
+ "str r3, [r0, r2]\n\t"
+ "sub r2, #4\n\t"
+ "bcs 2b\n\t"
+ "msr MSP, r3\n\t" /* Main (exception handler) stack. */
+ "ldr r0, [r1, #4]\n\t" /* Reset handler. */
+ "bx r0\n\t"
+ ".align 2\n"
+ "1: .word 0x20000000"
+ : /* no output */ : /* no input */ : "memory");
+#else
+ extern const uint32_t FT0[256], FT1[256], FT2[256];
+ asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
+ "ldr r0, 1f\n\t" /* r0 = SCR */
+ "mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */
+ "mov r2, #0x1000\n\t"
+ "add r1, r1, r2\n\t"
+ "sub r2, r2, #1\n\t"
+ "bic r1, r1, r2\n\t"
+ "str r1, [r0, #8]\n\t" /* Set SCR->VCR */
+ "ldr r0, [r1], #4\n\t"
+ "msr MSP, r0\n\t" /* Main (exception handler) stack. */
+ "ldr r0, [r1]\n\t" /* Reset handler. */
+ "bx r0\n\t"
+ ".align 2\n"
+ "1: .word 0xe000ed00"
+ : /* no output */ : /* no input */ : "memory");
+ /* Artificial entry to refer FT0, FT1, and FT2. */
+ asm volatile (""
+ : : "r" (FT0), "r" (FT1), "r" (FT2));
+#endif
+ /* Never reach here. */
+}
+
+typedef void (*handler)(void);
+extern uint8_t __ram_end__;
+
+handler vector[] __attribute__ ((section(".vectors"))) = {
+ (handler)&__ram_end__,
+ reset,
+ (handler)set_led,
+ flash_unlock,
+ (handler)flash_program_halfword,
+ (handler)flash_erase_page,
+ (handler)flash_check_blank,
+ (handler)flash_write,
+ (handler)flash_protect,
+ (handler)flash_erase_all_and_exec,
+ usb_lld_sys_init,
+ usb_lld_sys_shutdown,
+ nvic_system_reset,
+ clock_init,
+ gpio_init,
+ NULL,
+};
+
+const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
+ 3*2+2, /* bLength */
+ 0x03, /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
+ /* sys version: "3.0" */
+ '3', 0, '.', 0, '0', 0,
+};
+
+const uint32_t __attribute__((section(".sys.board_id")))
+sys_board_id = BOARD_ID;
+
+const uint8_t __attribute__((section(".sys.board_name")))
+sys_board_name[] = BOARD_NAME;
diff --git a/mcu/sys-stm32f030.h b/mcu/sys-stm32f030.h
new file mode 100644
index 0000000..4f18291
--- /dev/null
+++ b/mcu/sys-stm32f030.h
@@ -0,0 +1,134 @@
+#if defined(__ARM_ARCH_6M__)
+#define BOARD_ID_STM32F0_DISCOVERY 0xde4b4bc1
+#define BOARD_ID_FSM_55 0x83433c76
+#else
+#define BOARD_ID_CQ_STARM 0xc5480875
+#define BOARD_ID_FST_01_00 0x613870a9
+#define BOARD_ID_FST_01 0x696886af
+#define BOARD_ID_MAPLE_MINI 0x7a445272
+#define BOARD_ID_OLIMEX_STM32_H103 0xf92bb594
+#define BOARD_ID_STBEE_MINI 0x1f341961
+#define BOARD_ID_STBEE 0x945c37e8
+#define BOARD_ID_STM32_PRIMER2 0x21e5798d
+#define BOARD_ID_STM8S_DISCOVERY 0x2f0976bb
+#define BOARD_ID_ST_DONGLE 0x2cd4e471
+#define BOARD_ID_ST_NUCLEO_F103 0x9b87c16d
+#endif
+
+extern const uint8_t sys_version[8];
+extern const uint32_t sys_board_id;
+extern const uint8_t sys_board_name[];
+
+typedef void (*handler)(void);
+extern handler vector[16];
+
+static inline const uint8_t *
+unique_device_id (void)
+{
+ /* STM32F103 has 96-bit unique device identifier */
+ const uint8_t *addr = (const uint8_t *)0x1ffff7e8;
+
+ return addr;
+}
+
+static inline void
+set_led (int on)
+{
+ void (*func) (int) = (void (*)(int))vector[2];
+
+ return (*func) (on);
+}
+
+static inline void
+flash_unlock (void)
+{
+ (*vector[3]) ();
+}
+
+static inline int
+flash_program_halfword (uint32_t addr, uint16_t data)
+{
+ int (*func) (uint32_t, uint16_t) = (int (*)(uint32_t, uint16_t))vector[4];
+
+ return (*func) (addr, data);
+}
+
+static inline int
+flash_erase_page (uint32_t addr)
+{
+ int (*func) (uint32_t) = (int (*)(uint32_t))vector[5];
+
+ return (*func) (addr);
+}
+
+static inline int
+flash_check_blank (const uint8_t *p_start, size_t size)
+{
+ int (*func) (const uint8_t *, int) = (int (*)(const uint8_t *, int))vector[6];
+
+ return (*func) (p_start, size);
+}
+
+static inline int
+flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
+{
+ int (*func) (uint32_t, const uint8_t *, size_t)
+ = (int (*)(uint32_t, const uint8_t *, size_t))vector[7];
+
+ return (*func) (dst_addr, src, len);
+}
+
+static inline int
+flash_protect (void)
+{
+ int (*func) (void) = (int (*)(void))vector[8];
+
+ return (*func) ();
+}
+
+static inline void __attribute__((noreturn))
+flash_erase_all_and_exec (void (*entry)(void))
+{
+ void (*func) (void (*)(void)) = (void (*)(void (*)(void)))vector[9];
+
+ (*func) (entry);
+ for (;;);
+}
+
+static inline void
+usb_lld_sys_init (void)
+{
+ (*vector[10]) ();
+}
+
+static inline void
+usb_lld_sys_shutdown (void)
+{
+ (*vector[11]) ();
+}
+
+static inline void
+nvic_system_reset (void)
+{
+ (*vector[12]) ();
+}
+
+/*
+ * Users can override INLINE by 'attribute((used))' to have an
+ * implementation defined.
+ */
+#if !defined(INLINE)
+#define INLINE __inline__
+#endif
+
+static INLINE void
+clock_init (void)
+{
+ (*vector[13]) ();
+}
+
+static INLINE void
+gpio_init (void)
+{
+ (*vector[14]) ();
+}
diff --git a/mcu/sys-stm32f103.c b/mcu/sys-stm32f103.c
index 00ec8fe..dc1cfa1 100644
--- a/mcu/sys-stm32f103.c
+++ b/mcu/sys-stm32f103.c
@@ -17,7 +17,7 @@
#include <stdlib.h>
#include "board.h"
-#include "mcu/clk_gpio_init-stm32f103.c"
+#include "mcu/clk_gpio_init-stm32.c"
static void
diff --git a/mcu/sys-stm32f103.h b/mcu/sys-stm32f103.h
index aa7825d..7685f27 100644
--- a/mcu/sys-stm32f103.h
+++ b/mcu/sys-stm32f103.h
@@ -12,8 +12,10 @@
#define BOARD_ID_NITROKEY_START 0xad1e7ebd
extern const uint8_t sys_version[8];
+#if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)
extern const uint32_t sys_board_id;
extern const uint8_t sys_board_name[];
+#endif
typedef void (*handler)(void);
extern handler vector[16];
@@ -109,22 +111,18 @@ nvic_system_reset (void)
(*vector[12]) ();
}
-/*
- * Users can override INLINE by 'attribute((used))' to have an
- * implementation defined.
- */
-#if !defined(INLINE)
-#define INLINE __inline__
-#endif
+#ifdef REQUIRE_CLOCK_GPIO_SETTING_IN_SYS
+/* Provide the function entries. */
-static INLINE void
+static void __attribute__ ((used))
clock_init (void)
{
(*vector[13]) ();
}
-static INLINE void
+static void __attribute__ ((used))
gpio_init (void)
{
(*vector[14]) ();
}
+#endif
--
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