From c838e3f0e92f60023c95c1138e5fd5e95d24c7ea Mon Sep 17 00:00:00 2001
From: NIIBE Yutaka <gniibe@fsij.org>
Date: Thu, 6 Jun 2013 12:08:35 +0900
Subject: sys.h changes
---
example-cdc/Makefile | 2 +-
example-cdc/sys.c | 9 ++-------
example-cdc/sys.h | 20 ++++++++++++++++++++
3 files changed, 23 insertions(+), 8 deletions(-)
(limited to 'example-cdc')
diff --git a/example-cdc/Makefile b/example-cdc/Makefile
index 701aac3..b6c4c76 100644
--- a/example-cdc/Makefile
+++ b/example-cdc/Makefile
@@ -14,7 +14,7 @@ OBJCOPY = $(CROSS)objcopy
MCU = cortex-m3
CWARN = -Wall -Wextra -Wstrict-prototypes
-DEFS = -DFREE_STANDING
+DEFS = -DHAVE_SYS_H -DFREE_STANDING
OPT = -O3 -Os -g
LIBS =
diff --git a/example-cdc/sys.c b/example-cdc/sys.c
index af594b0..59d826b 100644
--- a/example-cdc/sys.c
+++ b/example-cdc/sys.c
@@ -21,10 +21,7 @@
#define CORTEX_PRIORITY_BITS 4
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
#define USB_LP_CAN1_RX0_IRQn 20
-#define STM32_USB_IRQ_PRIORITY 11
-
-#define FLASH_PAGE_SIZE 1024
-
+#define STM32_USB_IRQ_PRIORITY 11
#define STM32_SW_PLL (2 << 0)
@@ -336,9 +333,7 @@ flash_unlock (void)
#define intr_disable() asm volatile ("cpsid i" : : : "memory")
-
-#define intr_enable() asm volatile ("msr BASEPRI, %0\n\t" \
- "cpsie i" : : "r" (0) : "memory")
+#define intr_enable() asm volatile ("cpsie i" : : : "memory")
#define FLASH_SR_BSY 0x01
#define FLASH_SR_PGERR 0x04
diff --git a/example-cdc/sys.h b/example-cdc/sys.h
index 1f5b602..ce0eb1d 100644
--- a/example-cdc/sys.h
+++ b/example-cdc/sys.h
@@ -93,3 +93,23 @@ nvic_system_reset (void)
{
(*vector[12]) ();
}
+
+/*
+ * Users can override INLINE by 'attribute((used))' to have an
+ * implementation defined.
+ */
+#if !defined(INLINE)
+#define INLINE __inline__
+#endif
+
+static INLINE void
+clock_init (void)
+{
+ (*vector[13]) ();
+}
+
+static INLINE void
+gpio_init (void)
+{
+ (*vector[14]) ();
+}
--
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