From 48273b3cb60027d2a92f28f284e8ce8b1b276856 Mon Sep 17 00:00:00 2001
From: NIIBE Yutaka <gniibe@fsij.org>
Date: Mon, 22 Jun 2015 17:34:17 +0900
Subject: Clean up clock/gpio code
---
example-cdc/sys.c | 229 +-----------------------------------------------------
1 file changed, 2 insertions(+), 227 deletions(-)
(limited to 'example-cdc')
diff --git a/example-cdc/sys.c b/example-cdc/sys.c
index 264df5e..0f0c1ac 100644
--- a/example-cdc/sys.c
+++ b/example-cdc/sys.c
@@ -1,7 +1,7 @@
/*
* sys.c - system routines for the initial page for STM32F103.
*
- * Copyright (C) 2013, 2014 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015 Flying Stone Technology
* Author: NIIBE Yutaka <gniibe@fsij.org>
*
* Copying and distribution of this file, with or without modification,
@@ -17,53 +17,13 @@
#include <stdlib.h>
#include "board.h"
+#include "clk_gpio_init.c"
#define CORTEX_PRIORITY_BITS 4
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
#define USB_LP_CAN1_RX0_IRQn 20
#define STM32_USB_IRQ_PRIORITY 11
-
-#define STM32_SW_HSI (0 << 0)
-#define STM32_SW_PLL (2 << 0)
-#define STM32_PLLSRC_HSI (0 << 16)
-#define STM32_PLLSRC_HSE (1 << 16)
-
-#define STM32_PLLXTPRE_DIV1 (0 << 17)
-#define STM32_PLLXTPRE_DIV2 (1 << 17)
-
-#define STM32_HPRE_DIV1 (0 << 4)
-
-#define STM32_PPRE1_DIV1 (0 << 8)
-#define STM32_PPRE1_DIV2 (4 << 8)
-
-#define STM32_PPRE2_DIV1 (0 << 11)
-#define STM32_PPRE2_DIV2 (4 << 11)
-
-#define STM32_ADCPRE_DIV4 (1 << 14)
-#define STM32_ADCPRE_DIV6 (2 << 14)
-
-#define STM32_USBPRE_DIV1P5 (0 << 22)
-
-#define STM32_MCO_NOCLOCK (0 << 24)
-
-#define STM32_PPRE1 STM32_PPRE1_DIV2
-#define STM32_PLLSRC STM32_PLLSRC_HSE
-#define STM32_FLASHBITS 0x00000012
-#define STM32_PLLCLKIN (STM32_HSECLK / 1)
-
-#define STM32_SW STM32_SW_PLL
-#define STM32_HPRE STM32_HPRE_DIV1
-#define STM32_PPRE2 STM32_PPRE2_DIV1
-#define STM32_ADCPRE STM32_ADCPRE_DIV6
-#define STM32_MCOSEL STM32_MCO_NOCLOCK
-#define STM32_USBPRE STM32_USBPRE_DIV1P5
-
-#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK STM32_PLLCLKOUT
-#define STM32_HCLK (STM32_SYSCLK / 1)
-
struct NVIC {
uint32_t ISER[8];
uint32_t unused1[24];
@@ -93,191 +53,6 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
NVIC_ISER (n) = 1 << (n & 0x1F);
}
-
-#define PERIPH_BASE 0x40000000
-#define APBPERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
-
-struct RCC {
- volatile uint32_t CR;
- volatile uint32_t CFGR;
- volatile uint32_t CIR;
- volatile uint32_t APB2RSTR;
- volatile uint32_t APB1RSTR;
- volatile uint32_t AHBENR;
- volatile uint32_t APB2ENR;
- volatile uint32_t APB1ENR;
- volatile uint32_t BDCR;
- volatile uint32_t CSR;
-};
-
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN 0x00800000
-#define RCC_APB1RSTR_USBRST 0x00800000
-
-#define RCC_CR_HSION 0x00000001
-#define RCC_CR_HSIRDY 0x00000002
-#define RCC_CR_HSITRIM 0x000000F8
-#define RCC_CR_HSEON 0x00010000
-#define RCC_CR_HSERDY 0x00020000
-#define RCC_CR_PLLON 0x01000000
-#define RCC_CR_PLLRDY 0x02000000
-
-#define RCC_CFGR_SWS 0x0000000C
-#define RCC_CFGR_SWS_HSI 0x00000000
-
-#define RCC_AHBENR_CRCEN 0x0040
-
-#define RCC_APB2RSTR_AFIORST 0x00000001
-#define RCC_APB2RSTR_IOPARST 0x00000004
-#define RCC_APB2RSTR_IOPBRST 0x00000008
-#define RCC_APB2RSTR_IOPCRST 0x00000010
-#define RCC_APB2RSTR_IOPDRST 0x00000020
-
-#define RCC_APB2ENR_AFIOEN 0x00000001
-#define RCC_APB2ENR_IOPAEN 0x00000004
-#define RCC_APB2ENR_IOPBEN 0x00000008
-#define RCC_APB2ENR_IOPCEN 0x00000010
-#define RCC_APB2ENR_IOPDEN 0x00000020
-
-struct FLASH {
- volatile uint32_t ACR;
- volatile uint32_t KEYR;
- volatile uint32_t OPTKEYR;
- volatile uint32_t SR;
- volatile uint32_t CR;
- volatile uint32_t AR;
- volatile uint32_t RESERVED;
- volatile uint32_t OBR;
- volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void
-clock_init (void)
-{
- /* HSI setup */
- RCC->CR |= RCC_CR_HSION;
- while (!(RCC->CR & RCC_CR_HSIRDY))
- ;
- /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
- RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
- RCC->CFGR = 0;
- while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
- ;
-
- /* HSE setup */
- RCC->CR |= RCC_CR_HSEON;
- while (!(RCC->CR & RCC_CR_HSERDY))
- ;
-
- /* PLL setup */
- RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
- RCC->CR |= RCC_CR_PLLON;
- while (!(RCC->CR & RCC_CR_PLLRDY))
- ;
-
- /* Clock settings */
- RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
- | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
- /*
- * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
- */
-
- /* Flash setup */
- FLASH->ACR = STM32_FLASHBITS;
-
- /* CRC */
- RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
- /* Switching on the configured clock source. */
- RCC->CFGR |= STM32_SW;
- while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
- ;
-}
-
-
-struct AFIO
-{
- volatile uint32_t EVCR;
- volatile uint32_t MAPR;
- volatile uint32_t EXTICR[4];
- uint32_t RESERVED0;
- volatile uint32_t MAPR2;
-};
-
-#define AFIO_BASE 0x40010000
-static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
-
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
-#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
-
-
-struct GPIO {
- volatile uint32_t CRL;
- volatile uint32_t CRH;
- volatile uint32_t IDR;
- volatile uint32_t ODR;
- volatile uint32_t BSRR;
- volatile uint32_t BRR;
- volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOA ((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOB ((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOC ((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOD ((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOE ((struct GPIO *) GPIOE_BASE)
-
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-#ifdef GPIO_USB_BASE
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-#endif
-#ifdef GPIO_OTHER_BASE
-static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
-#endif
-
-static void
-gpio_init (void)
-{
- /* Enable GPIO clock. */
- RCC->APB2ENR |= RCC_ENR_IOP_EN;
- RCC->APB2RSTR = RCC_RSTR_IOP_RST;
- RCC->APB2RSTR = 0;
-
-#ifdef AFIO_MAPR_SOMETHING
- AFIO->MAPR |= AFIO_MAPR_SOMETHING;
-#endif
-
- GPIO_USB->ODR = VAL_GPIO_ODR;
- GPIO_USB->CRH = VAL_GPIO_CRH;
- GPIO_USB->CRL = VAL_GPIO_CRL;
-
-#if GPIO_USB_BASE != GPIO_LED_BASE
- GPIO_LED->ODR = VAL_GPIO_LED_ODR;
- GPIO_LED->CRH = VAL_GPIO_LED_CRH;
- GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-#endif
-
-#ifdef GPIO_OTHER_BASE
- GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
- GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
- GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
-#endif
-}
-
static void
usb_cable_config (int enable)
{
--
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