1 files changed, 16 insertions, 16 deletions
diff --git a/entry.c b/entry.c
index bd43d48..6539f24 100644
--- a/entry.c
+++ b/entry.c
@@ -1,7 +1,7 @@
 /*
  * entry.c - Entry routine when reset and interrupt vectors.
  *
- * Copyright (C) 2013, 2014 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015  Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -60,7 +60,7 @@
 
 #define STM32_MCO_NOCLOCK	(0 << 24)
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 #define STM32_PPRE1		STM32_PPRE1_DIV1
 #define STM32_PLLSRC		STM32_PLLSRC_HSI
 #define STM32_FLASHBITS		0x00000011
@@ -102,7 +102,7 @@ struct RCC {
   volatile uint32_t APB1ENR;
   volatile uint32_t BDCR;
   volatile uint32_t CSR;
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   volatile uint32_t AHBRSTR;
   volatile uint32_t CFGR2;
   volatile uint32_t CFGR3;
@@ -129,7 +129,7 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
 
 #define RCC_AHBENR_CRCEN        0x0040
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 #define RCC_AHBRSTR_IOPARST	0x00020000
 #define RCC_AHBRSTR_IOPBRST	0x00040000
 #define RCC_AHBRSTR_IOPCRST	0x00080000
@@ -158,7 +158,7 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
 #define RCC_APB2ENR_IOPDEN	0x00000020
 #endif
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 struct SYSCFG {
   volatile uint32_t CFGR1;
   uint32_t dummy0;
@@ -199,7 +199,7 @@ clock_init (void)
   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
     ;
 
-#if !MCU_STM32F0
+#if !defined(MCU_STM32F0)
   /* HSE setup */
   RCC->CR |= RCC_CR_HSEON;
   while (!(RCC->CR & RCC_CR_HSERDY))
@@ -231,7 +231,7 @@ clock_init (void)
   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
     ;
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
   RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
   RCC->APB2RSTR = 0;
@@ -242,7 +242,7 @@ clock_init (void)
 }
 
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 struct GPIO {
   volatile uint32_t MODER;
   volatile uint16_t OTYPER;
@@ -287,6 +287,7 @@ static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
 #define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
 
+
 struct GPIO {
   volatile uint32_t CRL;
   volatile uint32_t CRH;
@@ -321,7 +322,7 @@ static void __attribute__((used))
 gpio_init (void)
 {
   /* Enable GPIO clock. */
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   RCC->AHBENR |= RCC_ENR_IOP_EN;
   RCC->AHBRSTR = RCC_RSTR_IOP_RST;
   RCC->AHBRSTR = 0;
@@ -331,7 +332,7 @@ gpio_init (void)
   RCC->APB2RSTR = 0;
 #endif
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
   GPIO_LED->OTYPER  = VAL_GPIO_OTYPER;
   GPIO_LED->MODER   = VAL_GPIO_MODER;
@@ -381,7 +382,7 @@ static void nmi (void)
 
 static void hard_fault (void)
 {
-#if 1
+#if defined(__ARM_ARCH_6M__)
   register uint32_t primask;
 
   asm ("mrs	%0, PRIMASK" : "=r" (primask));
@@ -417,7 +418,7 @@ static void none (void)
 #define C_S_SUB(arg0, arg1, arg2) arg0 #arg1 arg2
 #define COMPOSE_STATEMENT(arg0,arg1,arg2)  C_S_SUB (arg0, arg1, arg2)
 
-#if MCU_STM32F0
+#if defined(__ARM_ARCH_6M__)
 __attribute__ ((used,section(".bss.startup.0")))
 uint32_t vectors_in_ram[48];
 #endif
@@ -436,7 +437,7 @@ void entry (void)
 	"0:\n\t"
 		"cmp	r1, r2\n\t"
 		"beq	1f\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"str	r0, [r1]\n\t"
 		"add	r1, #4\n\t"
 #else
@@ -451,7 +452,7 @@ void entry (void)
 	"2:\n\t"
 		"cmp	r1, r2\n\t"
 		"beq	3f\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"ldr	r0, [r3]\n\t"
 		"str	r0, [r1]\n\t"
 		"add	r3, #4\n\t"
@@ -473,8 +474,7 @@ void entry (void)
 		"bl	chx_systick_init\n\t"
 		"bl	gpio_init\n\t"
 		/* Enable interrupts.  */
-#if __ARM_ARCH_6M__
-#else
+#if defined(__ARM_ARCH_7M__)
 		"mov	r0, #0\n\t"
 		"msr	BASEPRI, r0\n\t"
 #endif