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-rw-r--r--entry.c137
1 files changed, 136 insertions, 1 deletions
diff --git a/entry.c b/entry.c
index 7abde4e..6539f24 100644
--- a/entry.c
+++ b/entry.c
@@ -1,7 +1,7 @@
/*
* entry.c - Entry routine when reset and interrupt vectors.
*
- * Copyright (C) 2013, 2014 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015 Flying Stone Technology
* Author: NIIBE Yutaka <gniibe@fsij.org>
*
* This file is a part of Chopstx, a thread library for embedded.
@@ -60,10 +60,17 @@
#define STM32_MCO_NOCLOCK (0 << 24)
+#if defined(MCU_STM32F0)
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#define STM32_PLLSRC STM32_PLLSRC_HSI
+#define STM32_FLASHBITS 0x00000011
+#define STM32_PLLCLKIN (STM32_HSICLK / 2)
+#else
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_FLASHBITS 0x00000012
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
+#endif
#define STM32_SW STM32_SW_PLL
#define STM32_HPRE STM32_HPRE_DIV1
@@ -95,6 +102,12 @@ struct RCC {
volatile uint32_t APB1ENR;
volatile uint32_t BDCR;
volatile uint32_t CSR;
+#if defined(MCU_STM32F0)
+ volatile uint32_t AHBRSTR;
+ volatile uint32_t CFGR2;
+ volatile uint32_t CFGR3;
+ volatile uint32_t CR2;
+#endif
};
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
@@ -116,6 +129,22 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
#define RCC_AHBENR_CRCEN 0x0040
+#if defined(MCU_STM32F0)
+#define RCC_AHBRSTR_IOPARST 0x00020000
+#define RCC_AHBRSTR_IOPBRST 0x00040000
+#define RCC_AHBRSTR_IOPCRST 0x00080000
+#define RCC_AHBRSTR_IOPDRST 0x00100000
+#define RCC_AHBRSTR_IOPFRST 0x00400000
+
+#define RCC_AHBENR_IOPAEN 0x00020000
+#define RCC_AHBENR_IOPBEN 0x00040000
+#define RCC_AHBENR_IOPCEN 0x00080000
+#define RCC_AHBENR_IOPDEN 0x00100000
+#define RCC_AHBENR_IOPFEN 0x00400000
+
+#define RCC_APB2RSTR_SYSCFGRST 0x00000001
+#define RCC_APB2ENR_SYSCFGEN 0x00000001
+#else
#define RCC_APB2RSTR_AFIORST 0x00000001
#define RCC_APB2RSTR_IOPARST 0x00000004
#define RCC_APB2RSTR_IOPBRST 0x00000008
@@ -127,6 +156,20 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
#define RCC_APB2ENR_IOPBEN 0x00000008
#define RCC_APB2ENR_IOPCEN 0x00000010
#define RCC_APB2ENR_IOPDEN 0x00000020
+#endif
+
+#if defined(MCU_STM32F0)
+struct SYSCFG {
+ volatile uint32_t CFGR1;
+ uint32_t dummy0;
+ volatile uint32_t EXTICR[4];
+ volatile uint32_t CFGR2;
+};
+#define SYSCFG_CFGR1_MEM_MODE 0x03
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
+#endif
struct FLASH {
volatile uint32_t ACR;
@@ -156,10 +199,12 @@ clock_init (void)
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
;
+#if !defined(MCU_STM32F0)
/* HSE setup */
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
;
+#endif
/* PLL setup */
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
@@ -185,9 +230,48 @@ clock_init (void)
RCC->CFGR |= STM32_SW;
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
+
+#if defined(MCU_STM32F0)
+ RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+ RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
+ RCC->APB2RSTR = 0;
+
+ /* Use vectors on RAM */
+ SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
+#endif
}
+#if defined(MCU_STM32F0)
+struct GPIO {
+ volatile uint32_t MODER;
+ volatile uint16_t OTYPER;
+ uint16_t dummy0;
+ volatile uint32_t OSPEEDR;
+ volatile uint32_t PUPDR;
+ volatile uint16_t IDR;
+ uint16_t dummy1;
+ volatile uint16_t ODR;
+ uint16_t dummy2;
+ volatile uint16_t BSRR;
+ uint16_t dummy3;
+ volatile uint32_t LCKR;
+ volatile uint32_t AFR[2];
+ volatile uint16_t BRR;
+ uint16_t dummy4;
+};
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
+#define GPIOA ((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
+#define GPIOB ((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
+#define GPIOC ((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
+#define GPIOD ((struct GPIO *) GPIOD_BASE)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
+#define GPIOF ((struct GPIO *) GPIOF_BASE)
+#else
struct AFIO
{
volatile uint32_t EVCR;
@@ -224,6 +308,7 @@ struct GPIO {
#define GPIOD ((struct GPIO *) GPIOD_BASE)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define GPIOE ((struct GPIO *) GPIOE_BASE)
+#endif
static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
#ifdef GPIO_USB_BASE
@@ -237,10 +322,29 @@ static void __attribute__((used))
gpio_init (void)
{
/* Enable GPIO clock. */
+#if defined(MCU_STM32F0)
+ RCC->AHBENR |= RCC_ENR_IOP_EN;
+ RCC->AHBRSTR = RCC_RSTR_IOP_RST;
+ RCC->AHBRSTR = 0;
+#else
RCC->APB2ENR |= RCC_ENR_IOP_EN;
RCC->APB2RSTR = RCC_RSTR_IOP_RST;
RCC->APB2RSTR = 0;
+#endif
+
+#if defined(MCU_STM32F0)
+ GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
+ GPIO_LED->OTYPER = VAL_GPIO_OTYPER;
+ GPIO_LED->MODER = VAL_GPIO_MODER;
+ GPIO_LED->PUPDR = VAL_GPIO_PUPDR;
+#ifdef GPIO_OTHER_BASE
+ GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
+ GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
+ GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
+ GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
+#endif
+#else
#ifdef AFIO_MAPR_SOMETHING
AFIO->MAPR |= AFIO_MAPR_SOMETHING;
#endif
@@ -260,6 +364,7 @@ gpio_init (void)
GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
#endif
+#endif
}
#endif
@@ -277,7 +382,18 @@ static void nmi (void)
static void hard_fault (void)
{
+#if defined(__ARM_ARCH_6M__)
+ register uint32_t primask;
+
+ asm ("mrs %0, PRIMASK" : "=r" (primask));
+
+ if (primask)
+ asm volatile ("b svc");
+ else
+ for (;;);
+#else
for (;;);
+#endif
}
static void mem_manage (void)
@@ -302,6 +418,11 @@ static void none (void)
#define C_S_SUB(arg0, arg1, arg2) arg0 #arg1 arg2
#define COMPOSE_STATEMENT(arg0,arg1,arg2) C_S_SUB (arg0, arg1, arg2)
+#if defined(__ARM_ARCH_6M__)
+__attribute__ ((used,section(".bss.startup.0")))
+uint32_t vectors_in_ram[48];
+#endif
+
/*
* This routine only changes PSP and not MSP.
*/
@@ -316,7 +437,12 @@ void entry (void)
"0:\n\t"
"cmp r1, r2\n\t"
"beq 1f\n\t"
+#if defined(__ARM_ARCH_6M__)
+ "str r0, [r1]\n\t"
+ "add r1, #4\n\t"
+#else
"str r0, [r1], #4\n\t"
+#endif
"b 0b\n"
"1:\n\t"
/* Copy data section. */
@@ -326,8 +452,15 @@ void entry (void)
"2:\n\t"
"cmp r1, r2\n\t"
"beq 3f\n\t"
+#if defined(__ARM_ARCH_6M__)
+ "ldr r0, [r3]\n\t"
+ "str r0, [r1]\n\t"
+ "add r3, #4\n\t"
+ "add r1, #4\n\t"
+#else
"ldr r0, [r3], #4\n\t"
"str r0, [r1], #4\n\t"
+#endif
"b 2b\n"
"3:\n\t"
/* Switch to PSP. */
@@ -341,8 +474,10 @@ void entry (void)
"bl chx_systick_init\n\t"
"bl gpio_init\n\t"
/* Enable interrupts. */
+#if defined(__ARM_ARCH_7M__)
"mov r0, #0\n\t"
"msr BASEPRI, r0\n\t"
+#endif
"cpsie i\n\t"
/* Call main. */
"mov r1, r0\n\t"
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-25 17:15:43 +0000