10 files changed, 171 insertions, 57 deletions
diff --git a/ChangeLog b/ChangeLog
index 655d70e..fd8dd7b 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,41 @@
+2015-04-20  Niibe Yutaka  <gniibe@fsij.org>
+
+	Merge cortex-m0-support branch.
+
+	* example-led/sys.c (gpio_init): Support MCU_STM32F0.
+	(reset): Support __ARM_ARCH_6M__.
+	* example-led/sample.ld: Change for Cortex-M0.
+
+	* example-fsm-55/*: New example for FSM-55.
+
+	* entry.c (STM32_PPRE1, STM32_PLLSRC, STM32_FLASHBITS)
+	(STM32_PLLCLKIN): Support MCU_STM32F0.
+	(struct RCC, RCC_*): Support MCU_STM32F0.
+	(struct SYSCFG) [MCU_STM32F0]: New.
+	(struct GPIO, GPIO*): Support MCU_STM32F0.
+	(clock_init, gpio_init): Support MCU_STM32F0.
+	(hard_fault, vectors_in_ram, entry): Support Cortex-M0.
+
+	* chopstx.c (chx_cpu_sched_lock, chx_cpu_sched_unlock)
+	(sched, preempt, svc): Support Cortex-M0.
+
+	* board/board-fsm-55.h: New.
+	* board/board-stm32f0-discovery.h: New.
+
+2015-04-17  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (CHX_PRIO_MAIN_INIT): New, removing CHX_PRIO_MAIN.
+	(chopstx_main_init): New.
+	(chx_init): Use CHX_PRIO_MAIN_INIT.
+
+2015-04-08  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-maple-mini.h: New from Aidan Thornton.
+
+2015-03-17  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.04a.
+
 2014-12-10  Niibe Yutaka  <gniibe@fsij.org>
 
 	* Version 0.04.
diff --git a/NEWS b/NEWS
index 18dd99c..d2d8d5c 100644
--- a/NEWS
+++ b/NEWS
@@ -1,5 +1,28 @@
 NEWS - Noteworthy changes
 
+* Major changes in Chopstx 0.05
+
+  Released 2015-04-20, by NIIBE Yutaka
+
+** New function: chopstx_main_init
+chopstx_main_init is the function to change the schedule priority of
+main thread.  This is useful to enter main loop after initialization
+of other threads.
+
+** The use of CHX_PRIO_MAIN
+CHX_PRIO_MAIN is deprecated.  Instead, please use the function
+chopstx_main_init.
+
+** Cortex-M0 support
+Cortex-M0 support has been added.
+
+** New board support: Maple mini
+It is contributed by Aidan Thornton.
+
+** New board support: FSM-55 and STM32F0 Discovery
+Those boards with STM32F0 (Cortex-M0) are now supported.
+
+
 * Major changes in Chopstx 0.04
 
   Released 2014-12-10, by NIIBE Yutaka
diff --git a/README b/README
index 451d726..da7b815 100644
--- a/README
+++ b/README
@@ -1,17 +1,17 @@
 Chopstx - Threads and only Threads
-							Version 0.04
-							  2014-12-10
+							Version 0.05
+							  2015-04-20
 							Niibe Yutaka
 					     Flying Stone Technology
 
 What's Chopstx?
 ===============
 
-Chopstx is an RT thread library for ARM Cortex-M3, specifically,
-STM32F103.
+Chopstx is an RT thread library for STM32F103 (ARM Cortex-M3)
+or STM32F0 (ARM Cortex-M0).
 
 While most RTOSes come with many features, drivers, and stacks,
-Chopstx just offers a RT thread library.
+Chopstx just offers a simple RT thread library.
 
 With Chopstx, interrupt handling is also done by a thread.  This
 enables coherent code for ease of maintenance.
@@ -39,9 +39,7 @@ USB CDC-ACM function.  You can build it like:
 Future Works
 ============
 
-We have a development branch for ARM Cortex-M0 and it works fine.
-It will be merged into mainline.
-
-Thread local storage and support of interface like poll/select would
-be next thing to be done.
+Convenience function to determine bottom of thread stack, thread local
+storage and support of interface like poll/select would be next thing
+to be done.
 -- 
diff --git a/VERSION b/VERSION
new file mode 100644
index 0000000..7a75098
--- /dev/null
+++ b/VERSION
@@ -0,0 +1 @@
+release/0.05
diff --git a/board/board-maple-mini.h b/board/board-maple-mini.h
new file mode 100644
index 0000000..92557e2
--- /dev/null
+++ b/board/board-maple-mini.h
@@ -0,0 +1,27 @@
+#define FLASH_PAGE_SIZE 1024
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
+
+#define GPIO_USB_CLEAR_TO_ENABLE        9
+#define GPIO_LED_SET_TO_EMIT            1
+
+/*
+ * Port B setup.
+ * PB1  - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * PB9  - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * ------------------------ Default
+ * PBx  - input with pull-up
+ */
+#define VAL_GPIO_ODR            0xFFFFFFFF
+#define VAL_GPIO_CRL            0x88888838      /*  PB7...PB0 */
+#define VAL_GPIO_CRH            0x88888838      /* PB15...PB8 */
+
+#define GPIO_USB_BASE   GPIOB_BASE
+#define GPIO_LED_BASE   GPIOB_BASE
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
+
+/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */
diff --git a/chopstx.c b/chopstx.c
index 3f27832..8224ba6 100644
--- a/chopstx.c
+++ b/chopstx.c
@@ -1,7 +1,7 @@
 /*
  * chopstx.c - Threads and only threads.
  *
- * Copyright (C) 2013, 2014 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015  Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -34,8 +34,8 @@
 /*
  * Thread priority: higer has higher precedence.
  */
-#if !defined(CHX_PRIO_MAIN)
-#define CHX_PRIO_MAIN 1
+#if !defined(CHX_PRIO_MAIN_INIT)
+#define CHX_PRIO_MAIN_INIT 1
 #endif
 #if !defined(CHX_FLAGS_MAIN)
 #define CHX_FLAGS_MAIN 0
@@ -61,22 +61,24 @@
 
 #define CPU_EXCEPTION_PRIORITY_CLEAR         0
 
-#if 0
-#define CPU_EXCEPTION_PRIORITY_SVC           0x30
+#if defined(__ARM_ARCH_6M__)
+#define CPU_EXCEPTION_PRIORITY_SVC           0x00
 
 #define CPU_EXCEPTION_PRIORITY_INHIBIT_SCHED 0x40
 /* ... */
 #define CPU_EXCEPTION_PRIORITY_SYSTICK       CPU_EXCEPTION_PRIORITY_INTERRUPT
-#define CPU_EXCEPTION_PRIORITY_INTERRUPT     0xb0
+#define CPU_EXCEPTION_PRIORITY_INTERRUPT     0x80
 #define CPU_EXCEPTION_PRIORITY_PENDSV        0xc0
-#else
-#define CPU_EXCEPTION_PRIORITY_SVC           0x00
+#elif defined(__ARM_ARCH_7M__)
+#define CPU_EXCEPTION_PRIORITY_SVC           0x30
 
 #define CPU_EXCEPTION_PRIORITY_INHIBIT_SCHED 0x40
 /* ... */
 #define CPU_EXCEPTION_PRIORITY_SYSTICK       CPU_EXCEPTION_PRIORITY_INTERRUPT
-#define CPU_EXCEPTION_PRIORITY_INTERRUPT     0x80
+#define CPU_EXCEPTION_PRIORITY_INTERRUPT     0xb0
 #define CPU_EXCEPTION_PRIORITY_PENDSV        0xc0
+#else
+#error "no support for this arch"
 #endif
 
 /**
@@ -226,7 +228,7 @@ chx_cpu_sched_lock (void)
 {
   if (running->prio < CHOPSTX_PRIO_INHIBIT_PREEMPTION)
     {
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
       asm volatile ("cpsid	i" : : : "memory");
 #else
       register uint32_t tmp = CPU_EXCEPTION_PRIORITY_INHIBIT_SCHED;
@@ -240,7 +242,7 @@ chx_cpu_sched_unlock (void)
 {
   if (running->prio < CHOPSTX_PRIO_INHIBIT_PREEMPTION)
     {
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
       asm volatile ("cpsie	i" : : : "memory");
 #else
       register uint32_t tmp = CPU_EXCEPTION_PRIORITY_CLEAR;
@@ -403,7 +405,7 @@ sched (void)
 		"ldr	r1, =running\n\t"
 		/* Update running.  */
 		"str	r0, [r1]\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"cmp	r0, #0\n\t"
 		"beq	1f\n\t"
 #else
@@ -412,7 +414,7 @@ sched (void)
 		/**/
 		"add	r0, #8\n\t"
 		"ldm	r0!, {r4, r5, r6, r7}\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"ldm	r0!, {r1, r2, r3}\n\t"
 		"mov	r8, r1\n\t"
 		"mov	r9, r2\n\t"
@@ -434,7 +436,7 @@ sched (void)
 		/**/
 		/* Unmask interrupts.  */
 		"mov	r0, #0\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"cpsie	i\n"
 #else
 		"msr	BASEPRI, r0\n"
@@ -450,7 +452,7 @@ sched (void)
 		"mov	r0, #0\n\t"
 		"mov	r1, #0\n\t"
 		"ldr	r2, =idle\n\t"	     /* PC = idle */
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"mov	r3, #0x010\n\t"
 		"lsl	r3, r3, #20\n\t" /* xPSR = T-flag set (Thumb) */
 #else
@@ -465,7 +467,7 @@ sched (void)
 		/**/
 		/* Unmask interrupts.  */
 		"mov	r0, #0\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"cpsie	i\n\t"
 #else
 		"msr	BASEPRI, r0\n\t"
@@ -483,14 +485,14 @@ preempt (void)
   tp = (struct chx_thread *)CPU_EXCEPTION_PRIORITY_INHIBIT_SCHED;
 
   asm (
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
        "cpsid	i\n\t"
 #else
        "msr	BASEPRI, r0\n\t"
 #endif
        "ldr	r1, =running\n\t"
        "ldr	r0, [r1]\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
        "cmp	r0, #0\n\t"
        "bne	0f\n\t"
 #else
@@ -501,7 +503,7 @@ preempt (void)
        "msr	MSP, r1\n\t"
        "b	sched\n"
   "0:\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
        "add	r1, r0, #4\n\t"
        "add	r1, #4\n\t"
 #else
@@ -559,7 +561,7 @@ svc (void)
 
   asm ("ldr	r1, =running\n\t"
        "ldr	r0, [r1]\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
        "add	r1, r0, #4\n\t"
        "add	r1, #4\n\t"
 #else
@@ -810,20 +812,42 @@ chx_init (struct chx_thread *tp)
   tp->flag_got_cancel = tp->flag_join_req = 0;
   tp->flag_sched_rr = (CHX_FLAGS_MAIN & CHOPSTX_SCHED_RR)? 1 : 0;
   tp->flag_detached = (CHX_FLAGS_MAIN & CHOPSTX_DETACHED)? 1 : 0;
-  tp->prio_orig = CHX_PRIO_MAIN;
+  tp->prio_orig = CHX_PRIO_MAIN_INIT;
   tp->prio = 0;
   tp->v = 0;
   running = tp;
 
-  if (CHX_PRIO_MAIN >= CHOPSTX_PRIO_INHIBIT_PREEMPTION)
+  if (CHX_PRIO_MAIN_INIT >= CHOPSTX_PRIO_INHIBIT_PREEMPTION)
     chx_cpu_sched_lock ();
 
-  tp->prio = CHX_PRIO_MAIN;
+  tp->prio = CHX_PRIO_MAIN_INIT;
 
   chopstx_main = (chopstx_t)tp;
 }
 
 
+/**
+ * chopstx_main_init - initialize main thread
+ * @prio: priority
+ *
+ * Initialize main thread with @prio.
+ * The thread main is created with priority CHX_PRIO_MAIN_INIT,
+ * and it runs with that priority until this routine will is called.
+ */
+void
+chopstx_main_init (chopstx_prio_t prio)
+{
+  struct chx_thread *tp = (struct chx_thread *)chopstx_main;
+
+  tp->prio_orig = prio;
+
+  if (prio >= CHOPSTX_PRIO_INHIBIT_PREEMPTION)
+    chx_cpu_sched_lock ();
+
+  tp->prio = prio;
+}
+
+
 static void
 chx_request_preemption (void)
 {
diff --git a/chopstx.h b/chopstx.h
index a7df3e8..cf8b233 100644
--- a/chopstx.h
+++ b/chopstx.h
@@ -31,6 +31,8 @@ typedef uint8_t chopstx_prio_t;
 
 extern chopstx_t chopstx_main;
 
+void chopstx_main_init (chopstx_prio_t);
+
 /* NOTE: This signature is different to PTHREAD's one.  */
 chopstx_t
 chopstx_create (uint32_t flags_and_prio,
diff --git a/entry.c b/entry.c
index bd43d48..6539f24 100644
--- a/entry.c
+++ b/entry.c
@@ -1,7 +1,7 @@
 /*
  * entry.c - Entry routine when reset and interrupt vectors.
  *
- * Copyright (C) 2013, 2014 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015  Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -60,7 +60,7 @@
 
 #define STM32_MCO_NOCLOCK	(0 << 24)
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 #define STM32_PPRE1		STM32_PPRE1_DIV1
 #define STM32_PLLSRC		STM32_PLLSRC_HSI
 #define STM32_FLASHBITS		0x00000011
@@ -102,7 +102,7 @@ struct RCC {
   volatile uint32_t APB1ENR;
   volatile uint32_t BDCR;
   volatile uint32_t CSR;
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   volatile uint32_t AHBRSTR;
   volatile uint32_t CFGR2;
   volatile uint32_t CFGR3;
@@ -129,7 +129,7 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
 
 #define RCC_AHBENR_CRCEN        0x0040
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 #define RCC_AHBRSTR_IOPARST	0x00020000
 #define RCC_AHBRSTR_IOPBRST	0x00040000
 #define RCC_AHBRSTR_IOPCRST	0x00080000
@@ -158,7 +158,7 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
 #define RCC_APB2ENR_IOPDEN	0x00000020
 #endif
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 struct SYSCFG {
   volatile uint32_t CFGR1;
   uint32_t dummy0;
@@ -199,7 +199,7 @@ clock_init (void)
   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
     ;
 
-#if !MCU_STM32F0
+#if !defined(MCU_STM32F0)
   /* HSE setup */
   RCC->CR |= RCC_CR_HSEON;
   while (!(RCC->CR & RCC_CR_HSERDY))
@@ -231,7 +231,7 @@ clock_init (void)
   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
     ;
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
   RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
   RCC->APB2RSTR = 0;
@@ -242,7 +242,7 @@ clock_init (void)
 }
 
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 struct GPIO {
   volatile uint32_t MODER;
   volatile uint16_t OTYPER;
@@ -287,6 +287,7 @@ static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
 #define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
 
+
 struct GPIO {
   volatile uint32_t CRL;
   volatile uint32_t CRH;
@@ -321,7 +322,7 @@ static void __attribute__((used))
 gpio_init (void)
 {
   /* Enable GPIO clock. */
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   RCC->AHBENR |= RCC_ENR_IOP_EN;
   RCC->AHBRSTR = RCC_RSTR_IOP_RST;
   RCC->AHBRSTR = 0;
@@ -331,7 +332,7 @@ gpio_init (void)
   RCC->APB2RSTR = 0;
 #endif
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
   GPIO_LED->OTYPER  = VAL_GPIO_OTYPER;
   GPIO_LED->MODER   = VAL_GPIO_MODER;
@@ -381,7 +382,7 @@ static void nmi (void)
 
 static void hard_fault (void)
 {
-#if 1
+#if defined(__ARM_ARCH_6M__)
   register uint32_t primask;
 
   asm ("mrs	%0, PRIMASK" : "=r" (primask));
@@ -417,7 +418,7 @@ static void none (void)
 #define C_S_SUB(arg0, arg1, arg2) arg0 #arg1 arg2
 #define COMPOSE_STATEMENT(arg0,arg1,arg2)  C_S_SUB (arg0, arg1, arg2)
 
-#if MCU_STM32F0
+#if defined(__ARM_ARCH_6M__)
 __attribute__ ((used,section(".bss.startup.0")))
 uint32_t vectors_in_ram[48];
 #endif
@@ -436,7 +437,7 @@ void entry (void)
 	"0:\n\t"
 		"cmp	r1, r2\n\t"
 		"beq	1f\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"str	r0, [r1]\n\t"
 		"add	r1, #4\n\t"
 #else
@@ -451,7 +452,7 @@ void entry (void)
 	"2:\n\t"
 		"cmp	r1, r2\n\t"
 		"beq	3f\n\t"
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
 		"ldr	r0, [r3]\n\t"
 		"str	r0, [r1]\n\t"
 		"add	r3, #4\n\t"
@@ -473,8 +474,7 @@ void entry (void)
 		"bl	chx_systick_init\n\t"
 		"bl	gpio_init\n\t"
 		/* Enable interrupts.  */
-#if __ARM_ARCH_6M__
-#else
+#if defined(__ARM_ARCH_7M__)
 		"mov	r0, #0\n\t"
 		"msr	BASEPRI, r0\n\t"
 #endif
diff --git a/example-led/Makefile b/example-led/Makefile
index 14ff7ff..89cbe21 100644
--- a/example-led/Makefile
+++ b/example-led/Makefile
@@ -13,7 +13,7 @@ LD   = $(CROSS)gcc
 OBJCOPY   = $(CROSS)objcopy
 
 # MCU   = cortex-m3
-MCU   = cortex-m0 # -save-temps
+MCU   = cortex-m0
 CWARN = -Wall -Wextra -Wstrict-prototypes
 DEFS  = -DHAVE_SYS_H -DFREE_STANDING -DMHZ=48
 # DEFS  = -DFREE_STANDING -DHAVE_SYS_H -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
diff --git a/example-led/sys.c b/example-led/sys.c
index c86a08e..84584f1 100644
--- a/example-led/sys.c
+++ b/example-led/sys.c
@@ -23,6 +23,7 @@
 #define USB_LP_CAN1_RX0_IRQn	 20
 #define STM32_USB_IRQ_PRIORITY   11
 
+
 #define STM32_SW_HSI		(0 << 0)
 #define STM32_SW_PLL		(2 << 0)
 #define STM32_PLLSRC_HSI	(0 << 16)
@@ -46,7 +47,7 @@
 
 #define STM32_MCO_NOCLOCK	(0 << 24)
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 #define STM32_PPRE1		STM32_PPRE1_DIV1
 #define STM32_PLLSRC		STM32_PLLSRC_HSI
 #define STM32_FLASHBITS		0x00000011
@@ -117,7 +118,7 @@ struct RCC {
   volatile uint32_t APB1ENR;
   volatile uint32_t BDCR;
   volatile uint32_t CSR;
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   volatile uint32_t AHBRSTR;
   volatile uint32_t CFGR2;
   volatile uint32_t CFGR3;
@@ -214,7 +215,7 @@ clock_init (void)
   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
     ;
 
-#if !MCU_STM32F0
+#if !defined(MCU_STM32F0)
   /* HSE setup */
   RCC->CR |= RCC_CR_HSEON;
   while (!(RCC->CR & RCC_CR_HSERDY))
@@ -246,7 +247,7 @@ clock_init (void)
   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
     ;
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
   RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
   RCC->APB2RSTR = 0;
@@ -257,7 +258,7 @@ clock_init (void)
 }
 
 
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
 struct GPIO {
   volatile uint32_t MODER;
   volatile uint16_t OTYPER;
@@ -337,7 +338,7 @@ static void
 gpio_init (void)
 {
   /* Enable GPIO clock. */
-#if MCU_STM32F0
+#if defined(MCU_STM32F0)
   RCC->AHBENR |= RCC_ENR_IOP_EN;
   RCC->AHBRSTR = RCC_RSTR_IOP_RST;
   RCC->AHBRSTR = 0;
@@ -698,7 +699,7 @@ reset (void)
    * This code may not be at the start of flash ROM, because of DFU.
    * So, we take the address from PC.
    */
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
   asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
 		"ldr	r0, 1f\n\t"     /* r0 = RAM start */
 		"mov	r1, pc\n\t"	/* r1 = (PC + 0x0400) & ~0x03ff */