diff options
| author | NIIBE Yutaka <gniibe@fsij.org> | 2014-12-10 16:18:29 +0900 |
|---|---|---|
| committer | NIIBE Yutaka <gniibe@fsij.org> | 2014-12-10 18:39:39 +0900 |
| commit | 23893d9b73ebc28ff111d21827122677c27bee55 (patch) | |
| tree | a887b7723395eb37abb244cbbd150dc7b4063e8d | |
| parent | 0276d0825ee27d1d5ecf238af0c9a2c053527125 (diff) | |
Version 0.04release/0.04
| -rw-r--r-- | ChangeLog | 20 | ||||
| -rw-r--r-- | NEWS | 11 | ||||
| -rw-r--r-- | README | 13 | ||||
| -rw-r--r-- | board/board-fst-01-00.h | 4 | ||||
| -rw-r--r-- | board/board-fst-01.h | 4 | ||||
| -rw-r--r-- | board/board-olimex-stm32-h103.h | 4 | ||||
| -rw-r--r-- | board/board-stbee-mini.h | 8 | ||||
| -rw-r--r-- | board/board-stbee.h | 4 | ||||
| -rw-r--r-- | board/board-stm8s-discovery.h | 4 | ||||
| -rw-r--r-- | chopstx.c | 19 | ||||
| -rw-r--r-- | doc/chopstx.texi | 2 | ||||
| -rw-r--r-- | entry.c | 68 | ||||
| -rw-r--r-- | example-cdc/sys.c | 70 | ||||
| -rw-r--r-- | example-led/sys.c | 70 |
14 files changed, 197 insertions, 104 deletions
@@ -1,3 +1,23 @@ +2014-12-10 Niibe Yutaka <gniibe@fsij.org> + + * Version 0.04. + * doc/chopstx.texi (VERSION): 0.04. + + * board/*.h: Updated. + + * example-cdc/sys.c: Copied from example-led. + + * example-led/sys.c (clock_init, GPIO_USB): Follow the change of + entry.c. + (gpio_init): Use RCC_ENR_IOP_EN and RCC_RSTR_IOP_RST. + (reset): Use ldr instead of mov.w and movt. + + * entry.c (GPIO_USB) [GPIO_USB_BASE]: Conditionally defined. + + * chopstx.c (preempt): Add ! for stm. + (chx_exit): Make sure RETVAL is saved onto r8. + (chopstx_usec_wait_var): Make sure USEC_P is saved onto r8. + 2013-11-27 Niibe Yutaka <gniibe@fsij.org> * board/board-stbee-mini.h: New. @@ -2,7 +2,16 @@ NEWS - Noteworthy changes * Major changes in Chopstx 0.04 - Released 2013-12-XX, by NIIBE Yutaka + Released 2014-12-10, by NIIBE Yutaka + +** new board.h macros and sys.c in example +In board.h, RCC_APB2ENR_IOP_EN was renamed to RCC_ENR_IOP_EN and +RCC_APB2RSTR_IOP_RST was renamed to RCC_RSTR_IOP_RST. Example sys.c +was changed accordingly. + +** Bug fix of chopstx_wakeup_usec_wait +chopstx_usec_wait_var/chopstx_usec_wait won't be woken up +by chopstx_wakeup_usec_wait. This is now fixed in 0.04. ** Board support STBee and STBee Mini The board STBee and STBee Mini are now supported. @@ -1,6 +1,6 @@ Chopstx - Threads and only Threads - Version 0.03 - 2013-11-08 + Version 0.04 + 2014-12-10 Niibe Yutaka Flying Stone Technology @@ -35,4 +35,13 @@ USB CDC-ACM function. You can build it like: $ ln -s ../board/board-olimex-stm32-h103.h board.h $ make + +Future Works +============ + +We have a development branch for ARM Cortex-M0 and it works fine. +It will be merged into mainline. + +Thread local storage and support of interface like poll/select would +be next thing to be done. -- diff --git a/board/board-fst-01-00.h b/board/board-fst-01-00.h index a2bf9f9..a00995e 100644 --- a/board/board-fst-01-00.h +++ b/board/board-fst-01-00.h @@ -25,7 +25,7 @@ #define GPIO_USB_BASE GPIOA_BASE #define GPIO_LED_BASE GPIOA_BASE -#define RCC_APB2ENR_IOP_EN RCC_APB2ENR_IOPAEN -#define RCC_APB2RSTR_IOP_RST RCC_APB2RSTR_IOPARST +#define RCC_ENR_IOP_EN RCC_APB2ENR_IOPAEN +#define RCC_RSTR_IOP_RST RCC_APB2RSTR_IOPARST /* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */ diff --git a/board/board-fst-01.h b/board/board-fst-01.h index 257ba72..40e98d7 100644 --- a/board/board-fst-01.h +++ b/board/board-fst-01.h @@ -58,8 +58,8 @@ #define GPIO_USB_BASE GPIOA_BASE #define GPIO_LED_BASE GPIOB_BASE -#define RCC_APB2ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN) -#define RCC_APB2RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST) +#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN) +#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST) /* NeuG settings for ADC2. */ #define NEUG_ADC_SETTING2_SMPR1 0 diff --git a/board/board-olimex-stm32-h103.h b/board/board-olimex-stm32-h103.h index a8cb7a0..07edfa5 100644 --- a/board/board-olimex-stm32-h103.h +++ b/board/board-olimex-stm32-h103.h @@ -25,8 +25,8 @@ #define GPIO_USB_BASE GPIOC_BASE #define GPIO_LED_BASE GPIOC_BASE -#define RCC_APB2ENR_IOP_EN RCC_APB2ENR_IOPCEN -#define RCC_APB2RSTR_IOP_RST RCC_APB2RSTR_IOPCRST +#define RCC_ENR_IOP_EN RCC_APB2ENR_IOPCEN +#define RCC_RSTR_IOP_RST RCC_APB2RSTR_IOPCRST /* NeuG settings for ADC2. */ #define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \ diff --git a/board/board-stbee-mini.h b/board/board-stbee-mini.h index 5e4acbb..9e92f66 100644 --- a/board/board-stbee-mini.h +++ b/board/board-stbee-mini.h @@ -78,9 +78,9 @@ #define GPIOB_7SEG_F 9 #define GPIOB_7SEG_G 8 -#define RCC_APB2ENR_IOP_EN \ +#define RCC_ENR_IOP_EN \ (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN) -#define RCC_APB2RSTR_IOP_RST \ +#define RCC_RSTR_IOP_RST \ (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST) #else /* @@ -97,8 +97,8 @@ #define VAL_GPIO_CRL 0x88888888 /* PA7...PA0 */ #define VAL_GPIO_CRH 0x63611888 /* PA15...PA8 */ -#define RCC_APB2ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN) -#define RCC_APB2RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_AFIORST) +#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN) +#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_AFIORST) #endif diff --git a/board/board-stbee.h b/board/board-stbee.h index 6c1f313..a12ec44 100644 --- a/board/board-stbee.h +++ b/board/board-stbee.h @@ -17,8 +17,8 @@ #define VAL_GPIO_OTHER_CRL 0x88888884 /* PA7...PA0 */ #define VAL_GPIO_OTHER_CRH 0x88811888 /* PA15...PA8 */ -#define RCC_APB2ENR_IOP_EN (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPDEN) -#define RCC_APB2RSTR_IOP_RST (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPDRST) +#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPDEN) +#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPDRST) /* * Port D setup. diff --git a/board/board-stm8s-discovery.h b/board/board-stm8s-discovery.h index 25b3e84..c4d52ea 100644 --- a/board/board-stm8s-discovery.h +++ b/board/board-stm8s-discovery.h @@ -39,9 +39,9 @@ #define GPIO_USB_BASE GPIOA_BASE #define GPIO_LED_BASE GPIOA_BASE -#define RCC_APB2ENR_IOP_EN \ +#define RCC_ENR_IOP_EN \ (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN) -#define RCC_APB2RSTR_IOP_RST \ +#define RCC_RSTR_IOP_RST \ (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST) /* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */ @@ -1,7 +1,7 @@ /* * chopstx.c - Threads and only threads. * - * Copyright (C) 2013 Flying Stone Technology + * Copyright (C) 2013, 2014 Flying Stone Technology * Author: NIIBE Yutaka <gniibe@fsij.org> * * This file is a part of Chopstx, a thread library for embedded. @@ -449,7 +449,7 @@ preempt (void) "mov r4, r10\n\t" "mov r5, r11\n\t" "mrs r6, PSP\n\t" /* r13(=SP) in user space. */ - "stm r1, {r2, r3, r4, r5, r6}" + "stm r1!, {r2, r3, r4, r5, r6}" : "=r" (tp) : "r" (tp) : "r1", "r2", "r3", "r4", "r5", "r6", "cc", "memory"); @@ -502,7 +502,7 @@ svc (void) "mov r4, r10\n\t" "mov r5, r11\n\t" "mrs r6, PSP\n\t" /* r13(=SP) in user space. */ - "stm r1, {r2, r3, r4, r5, r6}\n\t" + "stm r1!, {r2, r3, r4, r5, r6}\n\t" "ldr r1, [r6]" : "=r" (tp), "=r" (orig_r0) : /* no input */ @@ -777,9 +777,11 @@ chx_sched (uint32_t arg) static void __attribute__((noreturn)) chx_exit (void *retval) { - register uint32_t r8 asm ("r8") = (uint32_t)retval; + register uint32_t r8 asm ("r8"); struct chx_thread *q; + asm volatile ("mov %0, %1" : "=r" (r8) : "r" (retval)); + chx_cpu_sched_lock (); if (running->flag_join_req) { /* wake up a thread which requests to join */ @@ -917,14 +919,16 @@ chopstx_create (uint32_t flags_and_prio, void chopstx_usec_wait_var (uint32_t *var) { - register uint32_t *usec_p asm ("r8") = var; + register uint32_t *r8 asm ("r8"); + uint32_t *usec_p = var; uint32_t usec; uint32_t usec0 = 0; + asm volatile ("mov %0, %1" : "=r" (r8) : "r" (usec_p)); while (1) { chx_cpu_sched_lock (); - if (!usec_p) /* awakened */ + if (!r8) /* awakened */ break; *usec_p -= usec0; usec = *usec_p; @@ -937,8 +941,9 @@ chopstx_usec_wait_var (uint32_t *var) running->state = THREAD_WAIT_TIME; chx_timer_insert (running, usec0); chx_spin_unlock (&q_timer.lock); + asm volatile ("mov %0, %1" : "=r" (r8) : "r" (usec_p)); chx_sched (CHX_SLEEP); - asm ("" : "=r" (usec_p) : "r" (usec_p)); + asm ("" : "=r" (r8) : "r" (r8)); } chx_cpu_sched_unlock (); diff --git a/doc/chopstx.texi b/doc/chopstx.texi index e168c74..a8bbbef 100644 --- a/doc/chopstx.texi +++ b/doc/chopstx.texi @@ -1,7 +1,7 @@ \input texinfo @c -*-texinfo-*- @c %**start of header @setfilename chopstx.info -@set VERSION 0.03 +@set VERSION 0.04 @settitle Chopstx Reference Manual @c Unify some of the indices. @syncodeindex tp fn @@ -1,7 +1,7 @@ /* * entry.c - Entry routine when reset and interrupt vectors. * - * Copyright (C) 2013 Flying Stone Technology + * Copyright (C) 2013, 2014 Flying Stone Technology * Author: NIIBE Yutaka <gniibe@fsij.org> * * This file is a part of Chopstx, a thread library for embedded. @@ -33,10 +33,13 @@ #ifdef HAVE_SYS_H #define INLINE __attribute__ ((used)) #include "sys.h" +#include "board.h" #else #include "board.h" +#define STM32_SW_HSI (0 << 0) #define STM32_SW_PLL (2 << 0) +#define STM32_PLLSRC_HSI (0 << 16) #define STM32_PLLSRC_HSE (1 << 16) #define STM32_PLLXTPRE_DIV1 (0 << 17) @@ -44,6 +47,7 @@ #define STM32_HPRE_DIV1 (0 << 4) +#define STM32_PPRE1_DIV1 (0 << 8) #define STM32_PPRE1_DIV2 (4 << 8) #define STM32_PPRE2_DIV1 (0 << 11) @@ -56,26 +60,29 @@ #define STM32_MCO_NOCLOCK (0 << 24) -#define STM32_SW STM32_SW_PLL +#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_FLASHBITS 0x00000012 +#define STM32_PLLCLKIN (STM32_HSECLK / 1) + +#define STM32_SW STM32_SW_PLL #define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_ADCPRE STM32_ADCPRE_DIV6 #define STM32_MCOSEL STM32_MCO_NOCLOCK #define STM32_USBPRE STM32_USBPRE_DIV1P5 -#define STM32_PLLCLKIN (STM32_HSECLK / 1) #define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) #define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) #define STM32_SYSCLK STM32_PLLCLKOUT #define STM32_HCLK (STM32_SYSCLK / 1) -#define STM32_FLASHBITS 0x00000012 #define PERIPH_BASE 0x40000000 +#define APBPERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) struct RCC { volatile uint32_t CR; @@ -109,6 +116,18 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE); #define RCC_AHBENR_CRCEN 0x0040 +#define RCC_APB2RSTR_AFIORST 0x00000001 +#define RCC_APB2RSTR_IOPARST 0x00000004 +#define RCC_APB2RSTR_IOPBRST 0x00000008 +#define RCC_APB2RSTR_IOPCRST 0x00000010 +#define RCC_APB2RSTR_IOPDRST 0x00000020 + +#define RCC_APB2ENR_AFIOEN 0x00000001 +#define RCC_APB2ENR_IOPAEN 0x00000004 +#define RCC_APB2ENR_IOPBEN 0x00000008 +#define RCC_APB2ENR_IOPCEN 0x00000010 +#define RCC_APB2ENR_IOPDEN 0x00000020 + struct FLASH { volatile uint32_t ACR; volatile uint32_t KEYR; @@ -131,7 +150,8 @@ clock_init (void) RCC->CR |= RCC_CR_HSION; while (!(RCC->CR & RCC_CR_HSIRDY)) ; - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; + /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */ + RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION); RCC->CFGR = 0; while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) ; @@ -151,6 +171,10 @@ clock_init (void) RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + /* + * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR. + */ + /* Flash setup */ FLASH->ACR = STM32_FLASHBITS; @@ -163,18 +187,6 @@ clock_init (void) ; } -#define RCC_APB2RSTR_AFIORST 0x00000001 -#define RCC_APB2RSTR_IOPARST 0x00000004 -#define RCC_APB2RSTR_IOPBRST 0x00000008 -#define RCC_APB2RSTR_IOPCRST 0x00000010 -#define RCC_APB2RSTR_IOPDRST 0x00000020 - -#define RCC_APB2ENR_AFIOEN 0x00000001 -#define RCC_APB2ENR_IOPAEN 0x00000004 -#define RCC_APB2ENR_IOPBEN 0x00000008 -#define RCC_APB2ENR_IOPCEN 0x00000010 -#define RCC_APB2ENR_IOPDEN 0x00000020 - struct AFIO { @@ -213,8 +225,10 @@ struct GPIO { #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) #define GPIOE ((struct GPIO *) GPIOE_BASE) -static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE); static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE); +#ifdef GPIO_USB_BASE +static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE); +#endif #ifdef GPIO_OTHER_BASE static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE); #endif @@ -223,8 +237,8 @@ static void __attribute__((used)) gpio_init (void) { /* Enable GPIO clock. */ - RCC->APB2ENR |= RCC_APB2ENR_IOP_EN; - RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST; + RCC->APB2ENR |= RCC_ENR_IOP_EN; + RCC->APB2RSTR = RCC_RSTR_IOP_RST; RCC->APB2RSTR = 0; #ifdef AFIO_MAPR_SOMETHING @@ -250,6 +264,12 @@ gpio_init (void) #endif +extern uint8_t __main_stack_end__; +extern void svc (void); +extern void preempt (void); +extern void chx_timer_expired (void); +extern void chx_handle_intr (void); + static void nmi (void) { for (;;); @@ -334,12 +354,6 @@ void entry (void) typedef void (*handler)(void); -extern uint8_t __main_stack_end__; - -extern void svc (void); -extern void preempt (void); -extern void chx_timer_expired (void); -extern void chx_handle_intr (void); handler vector_table[] __attribute__ ((section(".startup.vectors"))) = { (handler)&__main_stack_end__, diff --git a/example-cdc/sys.c b/example-cdc/sys.c index 75fe7d2..264df5e 100644 --- a/example-cdc/sys.c +++ b/example-cdc/sys.c @@ -1,7 +1,7 @@ /* * sys.c - system routines for the initial page for STM32F103. * - * Copyright (C) 2013 Flying Stone Technology + * Copyright (C) 2013, 2014 Flying Stone Technology * Author: NIIBE Yutaka <gniibe@fsij.org> * * Copying and distribution of this file, with or without modification, @@ -24,7 +24,9 @@ #define STM32_USB_IRQ_PRIORITY 11 +#define STM32_SW_HSI (0 << 0) #define STM32_SW_PLL (2 << 0) +#define STM32_PLLSRC_HSI (0 << 16) #define STM32_PLLSRC_HSE (1 << 16) #define STM32_PLLXTPRE_DIV1 (0 << 17) @@ -32,6 +34,7 @@ #define STM32_HPRE_DIV1 (0 << 4) +#define STM32_PPRE1_DIV1 (0 << 8) #define STM32_PPRE1_DIV2 (4 << 8) #define STM32_PPRE2_DIV1 (0 << 11) @@ -44,23 +47,23 @@ #define STM32_MCO_NOCLOCK (0 << 24) -#define STM32_SW STM32_SW_PLL +#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_FLASHBITS 0x00000012 +#define STM32_PLLCLKIN (STM32_HSECLK / 1) + +#define STM32_SW STM32_SW_PLL #define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_ADCPRE STM32_ADCPRE_DIV6 #define STM32_MCOSEL STM32_MCO_NOCLOCK #define STM32_USBPRE STM32_USBPRE_DIV1P5 -#define STM32_PLLCLKIN (STM32_HSECLK / 1) #define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) #define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) #define STM32_SYSCLK STM32_PLLCLKOUT #define STM32_HCLK (STM32_SYSCLK / 1) -#define STM32_FLASHBITS 0x00000012 - struct NVIC { uint32_t ISER[8]; uint32_t unused1[24]; @@ -92,8 +95,10 @@ nvic_enable_vector (uint32_t n, uint32_t prio) #define PERIPH_BASE 0x40000000 +#define APBPERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) struct RCC { volatile uint32_t CR; @@ -127,6 +132,18 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE); #define RCC_AHBENR_CRCEN 0x0040 +#define RCC_APB2RSTR_AFIORST 0x00000001 +#define RCC_APB2RSTR_IOPARST 0x00000004 +#define RCC_APB2RSTR_IOPBRST 0x00000008 +#define RCC_APB2RSTR_IOPCRST 0x00000010 +#define RCC_APB2RSTR_IOPDRST 0x00000020 + +#define RCC_APB2ENR_AFIOEN 0x00000001 +#define RCC_APB2ENR_IOPAEN 0x00000004 +#define RCC_APB2ENR_IOPBEN 0x00000008 +#define RCC_APB2ENR_IOPCEN 0x00000010 +#define RCC_APB2ENR_IOPDEN 0x00000020 + struct FLASH { volatile uint32_t ACR; volatile uint32_t KEYR; @@ -149,7 +166,8 @@ clock_init (void) RCC->CR |= RCC_CR_HSION; while (!(RCC->CR & RCC_CR_HSIRDY)) ; - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; + /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */ + RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION); RCC->CFGR = 0; while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) ; @@ -169,6 +187,10 @@ clock_init (void) RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + /* + * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR. + */ + /* Flash setup */ FLASH->ACR = STM32_FLASHBITS; @@ -181,18 +203,6 @@ clock_init (void) ; } -#define RCC_APB2RSTR_AFIORST 0x00000001 -#define RCC_APB2RSTR_IOPARST 0x00000004 -#define RCC_APB2RSTR_IOPBRST 0x00000008 -#define RCC_APB2RSTR_IOPCRST 0x00000010 -#define RCC_APB2RSTR_IOPDRST 0x00000020 - -#define RCC_APB2ENR_AFIOEN 0x00000001 -#define RCC_APB2ENR_IOPAEN 0x00000004 -#define RCC_APB2ENR_IOPBEN 0x00000008 -#define RCC_APB2ENR_IOPCEN 0x00000010 -#define RCC_APB2ENR_IOPDEN 0x00000020 - struct AFIO { @@ -207,6 +217,7 @@ struct AFIO static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE; #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800 +#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000 struct GPIO { @@ -230,8 +241,10 @@ struct GPIO { #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) #define GPIOE ((struct GPIO *) GPIOE_BASE) -static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE); static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE); +#ifdef GPIO_USB_BASE +static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE); +#endif #ifdef GPIO_OTHER_BASE static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE); #endif @@ -240,8 +253,8 @@ static void gpio_init (void) { /* Enable GPIO clock. */ - RCC->APB2ENR |= RCC_APB2ENR_IOP_EN; - RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST; + RCC->APB2ENR |= RCC_ENR_IOP_EN; + RCC->APB2RSTR = RCC_RSTR_IOP_RST; RCC->APB2RSTR = 0; #ifdef AFIO_MAPR_SOMETHING @@ -577,10 +590,13 @@ reset (void) { extern const unsigned long *FT0, *FT1, *FT2; + /* + * This code may not be at the start of flash ROM, because of DFU. + * So, we take the address from PC. + */ asm volatile ("cpsid i\n\t" /* Mask all interrupts. */ - "mov.w r0, #0xed00\n\t" /* r0 = SCR */ - "movt r0, #0xe000\n\t" - "mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */ + "ldr r0, 1f\n\t" /* r0 = SCR */ + "mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */ "mov r2, #0x1000\n\t" "add r1, r1, r2\n\t" "sub r2, r2, #1\n\t" @@ -589,7 +605,9 @@ reset (void) "ldr r0, [r1], #4\n\t" "msr MSP, r0\n\t" /* Main (exception handler) stack. */ "ldr r0, [r1]\n\t" /* Reset handler. */ - "bx r0\n" + "bx r0\n\t" + ".align 2\n" + "1: .word 0xe000ed00" : /* no output */ : /* no input */ : "memory"); /* Never reach here. */ diff --git a/example-led/sys.c b/example-led/sys.c index 75fe7d2..264df5e 100644 --- a/example-led/sys.c +++ b/example-led/sys.c @@ -1,7 +1,7 @@ /* * sys.c - system routines for the initial page for STM32F103. * - * Copyright (C) 2013 Flying Stone Technology + * Copyright (C) 2013, 2014 Flying Stone Technology * Author: NIIBE Yutaka <gniibe@fsij.org> * * Copying and distribution of this file, with or without modification, @@ -24,7 +24,9 @@ #define STM32_USB_IRQ_PRIORITY 11 +#define STM32_SW_HSI (0 << 0) #define STM32_SW_PLL (2 << 0) +#define STM32_PLLSRC_HSI (0 << 16) #define STM32_PLLSRC_HSE (1 << 16) #define STM32_PLLXTPRE_DIV1 (0 << 17) @@ -32,6 +34,7 @@ #define STM32_HPRE_DIV1 (0 << 4) +#define STM32_PPRE1_DIV1 (0 << 8) #define STM32_PPRE1_DIV2 (4 << 8) #define STM32_PPRE2_DIV1 (0 << 11) @@ -44,23 +47,23 @@ #define STM32_MCO_NOCLOCK (0 << 24) -#define STM32_SW STM32_SW_PLL +#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_FLASHBITS 0x00000012 +#define STM32_PLLCLKIN (STM32_HSECLK / 1) + +#define STM32_SW STM32_SW_PLL #define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_ADCPRE STM32_ADCPRE_DIV6 #define STM32_MCOSEL STM32_MCO_NOCLOCK #define STM32_USBPRE STM32_USBPRE_DIV1P5 -#define STM32_PLLCLKIN (STM32_HSECLK / 1) #define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) #define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) #define STM32_SYSCLK STM32_PLLCLKOUT #define STM32_HCLK (STM32_SYSCLK / 1) -#define STM32_FLASHBITS 0x00000012 - struct NVIC { uint32_t ISER[8]; uint32_t unused1[24]; @@ -92,8 +95,10 @@ nvic_enable_vector (uint32_t n, uint32_t prio) #define PERIPH_BASE 0x40000000 +#define APBPERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) struct RCC { volatile uint32_t CR; @@ -127,6 +132,18 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE); #define RCC_AHBENR_CRCEN 0x0040 +#define RCC_APB2RSTR_AFIORST 0x00000001 +#define RCC_APB2RSTR_IOPARST 0x00000004 +#define RCC_APB2RSTR_IOPBRST 0x00000008 +#define RCC_APB2RSTR_IOPCRST 0x00000010 +#define RCC_APB2RSTR_IOPDRST 0x00000020 + +#define RCC_APB2ENR_AFIOEN 0x00000001 +#define RCC_APB2ENR_IOPAEN 0x00000004 +#define RCC_APB2ENR_IOPBEN 0x00000008 +#define RCC_APB2ENR_IOPCEN 0x00000010 +#define RCC_APB2ENR_IOPDEN 0x00000020 + struct FLASH { volatile uint32_t ACR; volatile uint32_t KEYR; @@ -149,7 +166,8 @@ clock_init (void) RCC->CR |= RCC_CR_HSION; while (!(RCC->CR & RCC_CR_HSIRDY)) ; - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; + /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */ + RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION); RCC->CFGR = 0; while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) ; @@ -169,6 +187,10 @@ clock_init (void) RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + /* + * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR. + */ + /* Flash setup */ FLASH->ACR = STM32_FLASHBITS; @@ -181,18 +203,6 @@ clock_init (void) ; } -#define RCC_APB2RSTR_AFIORST 0x00000001 -#define RCC_APB2RSTR_IOPARST 0x00000004 -#define RCC_APB2RSTR_IOPBRST 0x00000008 -#define RCC_APB2RSTR_IOPCRST 0x00000010 -#define RCC_APB2RSTR_IOPDRST 0x00000020 - -#define RCC_APB2ENR_AFIOEN 0x00000001 -#define RCC_APB2ENR_IOPAEN 0x00000004 -#define RCC_APB2ENR_IOPBEN 0x00000008 -#define RCC_APB2ENR_IOPCEN 0x00000010 -#define RCC_APB2ENR_IOPDEN 0x00000020 - struct AFIO { @@ -207,6 +217,7 @@ struct AFIO static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE; #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800 +#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000 struct GPIO { @@ -230,8 +241,10 @@ struct GPIO { #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) #define GPIOE ((struct GPIO *) GPIOE_BASE) -static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE); static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE); +#ifdef GPIO_USB_BASE +static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE); +#endif #ifdef GPIO_OTHER_BASE static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE); #endif @@ -240,8 +253,8 @@ static void gpio_init (void) { /* Enable GPIO clock. */ - RCC->APB2ENR |= RCC_APB2ENR_IOP_EN; - RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST; + RCC->APB2ENR |= RCC_ENR_IOP_EN; + RCC->APB2RSTR = RCC_RSTR_IOP_RST; RCC->APB2RSTR = 0; #ifdef AFIO_MAPR_SOMETHING @@ -577,10 +590,13 @@ reset (void) { extern const unsigned long *FT0, *FT1, *FT2; + /* + * This code may not be at the start of flash ROM, because of DFU. + * So, we take the address from PC. + */ asm volatile ("cpsid i\n\t" /* Mask all interrupts. */ - "mov.w r0, #0xed00\n\t" /* r0 = SCR */ - "movt r0, #0xe000\n\t" - "mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */ + "ldr r0, 1f\n\t" /* r0 = SCR */ + "mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */ "mov r2, #0x1000\n\t" "add r1, r1, r2\n\t" "sub r2, r2, #1\n\t" @@ -589,7 +605,9 @@ reset (void) "ldr r0, [r1], #4\n\t" "msr MSP, r0\n\t" /* Main (exception handler) stack. */ "ldr r0, [r1]\n\t" /* Reset handler. */ - "bx r0\n" + "bx r0\n\t" + ".align 2\n" + "1: .word 0xe000ed00" : /* no output */ : /* no input */ : "memory"); /* Never reach here. */ |